I know that we can generate all possible patterns using LFSR sequences but this will waste memory as we will have to store pattern to do error checking and storing all from 0 to 2^(n-1) will require huge memory. So instead of that I want some specific test patterns on which my trans receiver will be faulty. So are there any specific test patterns on which they will give error.
closed as unclear what you're asking by RoyC, Michel Keijzers, Dmitry Grigoryev, laptop2d, Finbarr Mar 20 '18 at 11:51
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You don't have to store the whole sequence. It's possible to feed a PRBS pattern back into a properly-configured linear feedback shift register and get a stream of bits at the output that indicate bit errors. When done with 'unrolled' LFSRs, this is quite efficient. See https://github.com/alexforencich/verilog-lfsr for code to implement both a PRBS generator and a PRBS checker, both of which have been verified to work on a Virtex Ultrascale FPGA at 25 Gbps. Also, the high speed transceivers on FPGAs will usually contain PRBS generators and checkers in hard logic for testing links. It should be possible to place the transceivers in the proper mode and read out the error counters through some combination of control lines and configuration ports.
As for corner cases for testing your receiver, the best I can recommend is just generating and checking a PRBS, especially without more knowledge of your design.