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I know that we can generate all possible patterns using LFSR sequences but this will waste memory as we will have to store pattern to do error checking and storing all from 0 to 2^(n-1) will require huge memory. So instead of that I want some specific test patterns on which my trans receiver will be faulty. So are there any specific test patterns on which they will give error.

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closed as unclear what you're asking by RoyC, Michel Keijzers, Dmitry Grigoryev, laptop2d, Finbarr Mar 20 '18 at 11:51

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You don't have to store the whole sequence. It's possible to feed a PRBS pattern back into a properly-configured linear feedback shift register and get a stream of bits at the output that indicate bit errors. When done with 'unrolled' LFSRs, this is quite efficient. See https://github.com/alexforencich/verilog-lfsr for code to implement both a PRBS generator and a PRBS checker, both of which have been verified to work on a Virtex Ultrascale FPGA at 25 Gbps. Also, the high speed transceivers on FPGAs will usually contain PRBS generators and checkers in hard logic for testing links. It should be possible to place the transceivers in the proper mode and read out the error counters through some combination of control lines and configuration ports.

As for corner cases for testing your receiver, the best I can recommend is just generating and checking a PRBS, especially without more knowledge of your design.

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  • \$\begingroup\$ What do you mean by feeding the PRBS pattern back into LFSR. I mean to ask how will you do error checking if you do not store the patterns ? \$\endgroup\$ – Akhil Singh Mar 19 '18 at 12:50
  • \$\begingroup\$ Can you describe how will you do error checking if you don't store all the patterns. \$\endgroup\$ – Akhil Singh Mar 19 '18 at 13:00
  • \$\begingroup\$ According to me test patterns should depend on speed, word size, encoding and clocking oh high speed signal. So how to design test patterns for that case ? \$\endgroup\$ – Akhil Singh Mar 19 '18 at 18:35
  • \$\begingroup\$ If the pattern is generated by an LFSR, then you can use a 'checker' LFSR that will output one 1 per tap for each bit error. All you need to do to get the error rate is count up the 1s and divide by the number of taps, so you'll want to add logic to count the number of 1s in each word and accumulate that. This works even for 2^31 PRBS, which is 2 Gb long. PRBS works just fine for any word size, each bit just ends up being a shifted copy of the same sequence. An 'unrolled' LFSR can generate or check whole words of output in each clock cycle. \$\endgroup\$ – alex.forencich Mar 19 '18 at 19:26
  • \$\begingroup\$ PRBS works for any clock speed and word size, and you can send it either directly or encoded if you like. I don't see how the clocking scheme should have an impact on the test pattern, anything you send is going to have to be properly clocked. It takes very little logic to generate and check PRBS data, no need for complex logic/state machines, large RAM, etc. which makes it a very common technique. Also, different sequences have different frequency characteristics and so test the link in different ways - i.e. making PRBS 7 work is much easier than PRBS 31. \$\endgroup\$ – alex.forencich Mar 19 '18 at 19:30

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