I have an FPGA design that uses 2 outside clocks (INCLK and TXCLK) from an ADC to latch data also coming from an ADC (TXOUT) and a system clock.
A defined INCLK TXCLK and clk_sys as primary clocks in the timing constraints editor.
When i run the timing analysis, it appears that i have old time violation.
1) there a hold time violation for the path between the registers of U3 (LMreceiver) and U2 (capture) so i thought if added some logic between these registers i would solve the problem , but nothing changes.
2) there is a hold time violation for paths inside the modules fifo_generator_1, these modules have been generated by the IP catalog so i cannot modify them.. Is there anything i can do?