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I have an FPGA design that uses 2 outside clocks (INCLK and TXCLK) from an ADC to latch data also coming from an ADC (TXOUT) and a system clock.

A defined INCLK TXCLK and clk_sys as primary clocks in the timing constraints editor.

When i run the timing analysis, it appears that i have old time violation.

1) there a hold time violation for the path between the registers of U3 (LMreceiver) and U2 (capture) so i thought if added some logic between these registers i would solve the problem , but nothing changes.

2) there is a hold time violation for paths inside the modules fifo_generator_1, these modules have been generated by the IP catalog so i cannot modify them.. Is there anything i can do?

My understanding of hold time violation is that we can fix them by introducing in the path some logic to delay the signalenter image description here enter image description here

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  • \$\begingroup\$ If INCLK and TXCLK are the outputs of the ADC and if TXCLK is a discontinuous clock as shown in the figure, do i have to define them as primary clocks in the timing wizard constraints? \$\endgroup\$ – the dude Mar 20 '18 at 9:27
  • \$\begingroup\$ your figure is not clear. Are U3 and U2 clocked by the same clock ? \$\endgroup\$ – Mitu Raj Mar 20 '18 at 17:07

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