1
\$\begingroup\$

I use a monoshot to extend the duration of a short duration pulse (few microseonds) to 150 milliseconds. The issue is that the monoshot undergoes false triggering in the absence of valid input:

The output of one such monoshot gets latched (Q = High and /Q = Low) and the latch goes away on cycling the power. The output of another monoshot in the same configuration alternates between High and Low from time to time.

I have probed the input of the monoshot with an oscilloscope in falling-edge trigger mode and found that the input is clean, free from spurious inputs.

Power supply is from a DC-DC converter with 5V output. On probing, the max switching noise is 0.2Vpp @ 12kHz. Fairly clean, I feel.

This is the datasheet of the monoshot, which according to the manufacturer is obsolete. I have a few of these lying around, hence using them for a hobby project.

enter image description here

Any ideas on what I might be doing wrong? Thanks!

\$\endgroup\$
  • 1
    \$\begingroup\$ A 10ns glitch on the output >0.5V outside your old noisy rails (50mv is better). may cause latchup as well as unterminated floating inputs withstray noise or even ground shift from ESD... \$\endgroup\$ – Tony Stewart Sunnyskyguy EE75 Mar 20 '18 at 7:08
  • 1
    \$\begingroup\$ Are you referring to the turning ON of the parasitic SCR in the CMOS (74HC) components? If yes, isn't it a phenomenon in which the Vcc gets shorted to ground through the parasitic SCR rather than the output stage (Q, /Q) getting latched? \$\endgroup\$ – Limpy Mar 20 '18 at 8:13
  • 1
    \$\begingroup\$ Yes and it can be triggered by both inputs or outputs or Vdd,Vss dropping inside same >0.5V meaning noise may contribute with distributed noise on Vss. Flip Flops on long wires are notorious antenna for noise glitches that can even toggle the output from external glitches and worst case cause SCR shootthru AND/OR latching or failure of internal functions, always buffer FF outputs on long wires or use twisted pairs with Gnd. (long wires are what some hobbyists are prone to use is just an assumption here) \$\endgroup\$ – Tony Stewart Sunnyskyguy EE75 Mar 20 '18 at 14:21
1
\$\begingroup\$

While your schematic is incomplete (it does not show the other half of the IC), this may be the problem. CMOS MUST have all unused inputs tied to ground or Vcc. That goes for unused portions of an IC as well as unused inputs to a particular function. So ground pins 9, 10, and 11.

While you're at it, ground 14 as well. See Figure 13 of the data sheet.

\$\endgroup\$
  • \$\begingroup\$ The other part of the IC is connected to an input and output in identical configuration as shown in the schematic and there are no unused inputs or outputs. I should've mentioned it. But pins 6 & 14 are not grounded in the layout. Good catch. I guess that could be a reason for the output to toggle. But latching can't be due to that, right? \$\endgroup\$ – Limpy Mar 21 '18 at 7:21

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.