Question on use of clock in SDC style IO delay constraints
The intention of this write up is to cast some clarity on how an FPGA IO interface has to be constrained. As a preamble the two timing constraints which can be used for constraining an FPGA IO interface are:
Usage: set_input_delay [-add_delay] -clock [-clock_fall] [-fall] [-max] [-min] [- reference_pin ] [-rise] [-source_latency_included]
Usage: set_output_delay [-add_delay] -clock [-clock_fall] [-fall] [-max] [-min] [- reference_pin ] [-rise] [-source_latency_included]
The set_input_delay constraint makes sure that an input to the FPGA from an external chip meets the internal setup and hold requirements. Similarly the set_output_delay makes sure that the data driven from an FPGA meets the setup and hold requirements of the external chip. The constraints use various timings like [tCO tSU tH] of the external chip, PCB trace delay, clock skew etc for the estimation. These stuff are pretty clear to me except the "use of clock". Here starts the confusion!
Both the constraints specify the delay values with respect to a clock. Now comes the concept of a virtual clock, a clock which feeds the external chip and not existent inside the FPGA. I have seen Intel FPGA(previously Altera) documentations prescribing the use of a Virtual Clock for constraining all IO interfaces. But it did not make complete sense to me till now!
Regarding the clocking, there are two cases I'm interested in. Please check the attachement for the drawings.
Case 1: If I have source synchronous interface like an SDRAM or QSPI interface the FPGA internally generates the clock for the external chip. In the figure clk_ext and data are sent from the FPGA. So should the SDC constrainting use a virtual clock or a generated clock from FPGA?
Case 2: There is an external clock synthesizer feeding the FPGA and the ASIC clocks. The clocks clk_osc_fpga and clk_osc_asic may or maynot be related as far as we are concerned. But there is indeed a data flow from the FPGA -> ASIC. Note that the data generation inside FPGA is done using clk_int which is not sent out! So is this where we should use a virtual clock? And how would the timing analyzer model the skews or frequency differences in the virtual clock with respect to the internal fpga clock?
I would appreciate any advice on this. And thanks for reading a really long question.
Update on the Question:
In one of the designs, I was able to estimate the latency of the clk_int with respect to the clk_osc_fpga. I found it to be around -1.3ns. So basically this means that the virtual clock or clk_osc_asic is propagated advance with respect to fpga internal clock clk_int. The question is how do I constrain this latency? Should I use the set_clock_latency on the virtual clock? Or just adjust the phase of the virtual clock when using create_clock constraint? Also how to specify the sampling edge of the virtual clock?
Thanks again for the support.