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This is somewhat related to my previous question regarding why I wasn't seeing a clamp biasing effect with my JFET Vackar oscillator. I think I figured it out and I'm wondering if you guys agree. Below is a sketch of what I saw on the scope (it's a bit busy, apologies for that!): enter image description here

enter image description here

As you can (hopefully) see, the gate voltage peaks at 1.2V before falling to -2V (the subject of my previous question). But, look at the source current measured across the 1 ohm resistor. It seems to flow towards the gate! Not at all what I was expecting. I believe that what I'm seeing is the effect of parasitic gate-source capacitance and its effect at this frequency (~38MHz).

What's interesting is that this effect seems to negate any clamping effect and with the gate voltage now rising to 1.2V, it might account for the other surprising aspect: the source current peaks at over 120mA. That's way higher then this JFETs Idss (16mA measured).

I should really put this bit in a separate question, but what the heck. At the end of the day, I'm trying to estimate the output amplitude of this oscillator and I'm not having much luck. Clarke & Hess offered a reasonable solution for JFET circuits where the sine wave at the gate was clamped to zero, but this effect I'm seeing makes this route a bit trickier.

Does anyone know of a straightforward way of computing the amplitude of this oscillator that doesn't involve simulation? I'm not against simulation per say, but you need to set things up right and it tends to obscure the complexities that makes a deeper understanding possible (my opinion).

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  • \$\begingroup\$ Your 'scope interpretations look deceiving. It is rather hard to probe properly @ 38 Mhz. A good 'scope with something like 200 MHz bandwidth is required too. \$\endgroup\$
    – glen_geek
    Mar 20, 2018 at 14:36
  • \$\begingroup\$ Yes, I considered that and it's possible. In fact, I'm sure the probe capacitance is adding to this also. However, I measured the drain current and it had peak currents comparable to the source. So, what would cause the JFET to draw that level of current? \$\endgroup\$
    – Buck8pe
    Mar 20, 2018 at 14:42
  • \$\begingroup\$ And if it's fair to say that a high voltage at the gate is letting more current (higher density maybe) flow through the channel, then we should ask, why is the gate voltage not clamping near zero? \$\endgroup\$
    – Buck8pe
    Mar 20, 2018 at 14:49
  • \$\begingroup\$ WHen Vgs >0 , it spikes L1 then L2 and pumps resonance. May work better with better supply choke and better model. This one has ideal passives tinyurl.com/y8hqzkeg \$\endgroup\$
    – Tony Stewart EE75
    Mar 20, 2018 at 15:35
  • \$\begingroup\$ It's hard to read the output voltage in that sim Tony, but I glimpsed a reading of 25V. The actual circuit output (taken from JFET drain) is 4Vpp with a DC bias of 12V. \$\endgroup\$
    – Buck8pe
    Mar 20, 2018 at 15:54

2 Answers 2

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This is not intended to answer all your questions, rather give more insight.

This MSc Thesis may help see how the non-linear approach used by Clarke & Hess works for different RF oscillator designs.

Oscillator Phase Noise Reduction Using Nonlinear Design Techniques
by David S. M. Steinbach 2001

Taking the Fourier transform of a pulse or series of pulses in the time domain yields a number of frequency components.

This harmonic trade-off is an important consideration in reducing noise content by using shorter pulses.

Examples are given for CB CE and CC configurations of oscillators.

Accurate models are needed for simulation and calculations get messy. enter image description here

Good reference on Oscillator Phase Noise
http://rfic.eecs.berkeley.edu/~niknejad/ee242/pdf/eecs242_lect22_phasenoise.pdf

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  • \$\begingroup\$ Thanks Tony, that's exactly what I was attempting to measure with my source and drain resistors - the pulse train through the fet. I was going to compare what I saw there against a calculated approach using the C&H fundamental harmonic equation for signals biased outside the square-law region. \$\endgroup\$
    – Buck8pe
    Mar 20, 2018 at 18:45
  • \$\begingroup\$ Unfortunately, what I see in the actual circuit is much more complicated, since it's clearly pushing the gate voltage higher than 0V. Also, it would seem the conduction angle is much wider than expected. I suspect my loop-gain equation is also invalid owing to unaccounted for parasitics. \$\endgroup\$
    – Buck8pe
    Mar 20, 2018 at 18:48
  • \$\begingroup\$ tinyurl.com/yc7na5bj I also saw sharp current pulses in Simulator with your original circuit. \$\endgroup\$
    – Tony Stewart EE75
    Mar 20, 2018 at 19:03
  • \$\begingroup\$ Yep, that's what I was expecting to see, but I'm just not seeing it in the circuit on the board (copper clad, short leads). Instead, I'm seeing a gate voltage that mainly drives the fet DS junction into conduction, widening the conduction angle so that it looks sine like and it's flowing quite a bit of current at the peaks too. Not expected at all. \$\endgroup\$
    – Buck8pe
    Mar 20, 2018 at 19:04
  • \$\begingroup\$ I'm only seeing <10mW across the FET but almost 40VAR in the Pi resonator while the positive spikes pump the 1mH choke to supply the reactive power just to the reactive parts tinyurl.com/yb6j7usz \$\endgroup\$
    – Tony Stewart EE75
    Mar 20, 2018 at 19:18
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The FET gate is a diode. Normally it is kept reverse biased or at least below the 0.5 - 0.6 volt positive bias with respect to the source where it would start to conduct. Obviously it will start clamping the tuned circuit if the signal voltage gets too high.

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