This is somewhat related to my previous question regarding why I wasn't seeing a clamp biasing effect with my JFET Vackar oscillator. I think I figured it out and I'm wondering if you guys agree. Below is a sketch of what I saw on the scope (it's a bit busy, apologies for that!):
As you can (hopefully) see, the gate voltage peaks at 1.2V before falling to -2V (the subject of my previous question). But, look at the source current measured across the 1 ohm resistor. It seems to flow towards the gate! Not at all what I was expecting. I believe that what I'm seeing is the effect of parasitic gate-source capacitance and its effect at this frequency (~38MHz).
What's interesting is that this effect seems to negate any clamping effect and with the gate voltage now rising to 1.2V, it might account for the other surprising aspect: the source current peaks at over 120mA. That's way higher then this JFETs Idss (16mA measured).
I should really put this bit in a separate question, but what the heck. At the end of the day, I'm trying to estimate the output amplitude of this oscillator and I'm not having much luck. Clarke & Hess offered a reasonable solution for JFET circuits where the sine wave at the gate was clamped to zero, but this effect I'm seeing makes this route a bit trickier.
Does anyone know of a straightforward way of computing the amplitude of this oscillator that doesn't involve simulation? I'm not against simulation per say, but you need to set things up right and it tends to obscure the complexities that makes a deeper understanding possible (my opinion).