# Interpreting results when IC temperature fits all categories

I have recently downloaded a datasheet for one of the chips I am using in my project, the familiar 74HC164 shift register. The datsheet URL is here:

https://assets.nexperia.com/documents/data-sheet/74HC_HCT164.pdf

So I then look inside it to try to figure out how long the chip needs to process various states, and it provides three temperature categories as circled in the picture:

Since my circuit never overheats, and runs in a normal room temperature environment, I find this particular datasheet confusing. It's because my scenario fits two temperature categories and possibly three. To me, room temperature is 21 degrees, so the only category that MIGHT not apply to me is the 25 degrees celcius category.

Let's say I wanted to determine Propogation delay based on the information given. What value should I use?

1. The worst case of 255ns (because the temp range is -40 to +125 degrees)?

OR

1. Do I need a special (tell me its not expensive) thermometer to measure the degree range of my chip while its running and get results based on the temperature range that special thermometer reports?

OR

1. I should assume these temperatures mean the maximum rise temperature of the circuit when it is running and follow the 25 degrees column?

Or is there another way to calculate the value based on the chip not warming up at all even with the correct power applied to it and the whole circuit being in a room at room temperature?

Technically, if you are not running exactly at 25C, you need to use the maximum value for -40C to 85C since that's the smallest bucket that fits your temperature (assuming your board doesn't heat up too much and you aren't doing something like running your board at 75C or 80C ambient), so 215ns is what you need to use. However, that only applies if you are running at 2.0V. Increase that to 4.5V and you're at 43ns.

In reality, the propagation delay will probably be around the typical value, with the maximum at 170ns since you are slightly under 25C and circuits tend to heat up when they are in use.

The other thing to keep in mind is that those maximums are very conservative in most cases. They account for both temperature corners and process variations. You may find that your actual propagation delay is quite a bit smaller than the maximum.

If you're super concerned about propagation delay you can:

1. Measure the propagation delay of that IC on every board. This isn't unheard of and for precision equipment there is almost always a part that needs to be characterized per board for calibration purposes. You'll need to heat your board and cool your board in an environmental chamber too, unless you only specify that it will run in spec at a particular ambient temperature.

2. Measure a sampling of ICs and give yourself enough "warm fuzzies" that the maximum propagation delay will be around some value.

3. Find a shift register that has tighter specifications. You can do this either by using an actual part or implementing it in an FPGA or CPLD and constraining the synthesis tools so that they meet the specifications you want.

4. Design your board so that it meets timing with the absolute worst specs. (You should really do this anyway, even if you weren't super concerned)

If I were super concerned about propagation delay, I would go with either option 1, 3, and 4 with my preference being for options 3 and 4.

Side note, if you want to measure temperature for the chip and find out your actual temperature range, you just need a thermocouple glued to the case of the IC or hovering in the air. They come with many multimeters these days and are quite cheap.

• Ok I was initially thinking using the worst case value but I wanted to make sure. – Mike Mar 23 '18 at 20:08

Your temperature will vary in this CMOS implementation, primarily because of a) slow input clocks that allow lots of shoot-thru currents when both the NFETs and the PFETs are --- briefly --- on, and a CROWBAR current flows; expect 1mmilliAmp per logic gate inside the IC that is changing state (you should place a 1 ohm resistor from a 0.1uF SurfaceMount capacitor to the VDD pin, and monitor the voltage drop --- set the scope on AC --- across the 1 ohm). b) heavy capacitive loads on the various outputs; power due to capacitive loads is computed as 0.5 * Capacitance * Frequency * VDD * VDD; at 100pF and 10MHz and 5 volts, the power is 0.5 * 1e-10 * 1e+7 * 5 * 5 = 12.5 milliWatts per output; this power is both dissipated inside those tiny FETS driving the load and is power available to the capacitor outside the IC

Note a variation in VDD from 4.5v to 5.5 volt causes 20% variation in power.

• Are you sure about the 0.5 there, for power? Assuming sharp edges, I get \begin{align*}P_\text{AVG}&={1\over T}\left(\int_0^{T\over 2}\left[V_\text{OUT}\cdot -C_L\cdot{\text{d} V_\text{OUT}\over\text{d}x}\right]\text{d}t+\int_{T\over 2}^T\left[\left(V_\text{DD}-V_\text{OUT}\right)\cdot C_L\cdot{\text{d} V_\text{OUT}\over\text{d}x}\right]\text{d}t\right)\\\\&={1\over T}C_L\:V_\text{DD}^2\\\\&=f \:C_L \:V_\text{DD}^2\end{align*} – jonk Mar 21 '18 at 5:54