# First or last value checker component/funtion [closed]

I am trying to make a circuit that can store the first and last value from a series of values. To do this I'm guessing I need a component to determine if it's the first or last value and this is what I'm struggling to find.

The data is arriving from an ADC, which is converting a spiromoteter analogue signal into digital. Each binary value of flow is inputted on a bus (with bits in parallel). My aim is to do numerical integration (Simpson's rule) for this I need to add the first and last values together.

Thank you.

• Way too little information. How does the data arrive (is there a valid signal etc etc), in what format, when does the sender know what is the last input, what is the level of detail you need the answer to be etc. – DonFusili Mar 21 '18 at 12:53
• Define first and last. Storing something is easy; retrieving it can be more problematic. A series of inputs - a plurality of inputs? – Andy aka Mar 21 '18 at 12:53
• You need to provide a lot more detail about the nature of the data stream, e.g. voltage levels, timing, what separates different series of inputs, etc. before this question can be answered. – crj11 Mar 21 '18 at 12:55
• What's the protocol for the ADC datastream? – DonFusili Mar 21 '18 at 13:00
• Thank you for your replies, I have added more detail. If you need to know anything else, let me know. – Redjman Mar 21 '18 at 13:01

Assuming you're sure you need this, your code would probably look something like this:

p_main: process(clk, reset_n)

type flowstate is (initial, gathering);
variable r_state : flowstate;

variable r_first_val : integer range 0 to c_max;
variable r_second_val : integer range 0 to c_max;

begin

if reset_n = '0' then
r_state := initial;
r_first_val := 0;
r_second_val := 0;
first_val_output_signal <= 0;
second_val_output_signal <= 0;
elsif rising_edge(clk) then
-- determine if the input is valid, depends on protocol
if inputsvalid then
case r_state is
when initial =>
r_state := gathering;
when gathering =>
-- determine if the gathering is done, depends on protocol
if finished_gathering then
r_state := initial;
-- go back to initial state
first_val_output_signal <= r_first_val;
second_val_output_signal <= r_second_val;
end if;
end case;
end if;
end if;

end process;


As you can see, much would depend on the actual protocol the data uses. You mention a bus, but not what kind of bus. Determining what data is valid and how to signal to other blocks/processes that you updated the output signals depends on your application.