What determines the acquisition time of a sample and hold circuit?

For example if I had wanted to design a circuit that samples at every 0.1 second intervals what would limit and affect the desired acquisition time?

Would it just be how long the capacitor takes to charge? Or are other factors involved

  • \$\begingroup\$ I'm unclear. Do you want your sample and hold circuit to integrate the signal over the whole 0.1 seconds (100milli seconds), or do you want to sample the signal as fast as practical (say sample in 1 micro second) but only do that every 0.1 seconds? Can you understand that they may be different? \$\endgroup\$ – gbulmer Mar 21 '18 at 15:43
  • \$\begingroup\$ @gbulmer Yes sorry, I will edit the question, I want to sample the signal as fast as possible but only do that every 0.1 seconds. \$\endgroup\$ – user131618 Mar 21 '18 at 15:45
  • \$\begingroup\$ The acquisition time depends primarily on the value of the hold capacitor, the effective resistance and the speed of the actual switch. \$\endgroup\$ – Peter Smith Mar 21 '18 at 15:48
  • \$\begingroup\$ Fast acquisition time and long hold time are competing issues; relatively long hold times need a bit of care (and the correct type of hold cap). \$\endgroup\$ – Peter Smith Mar 21 '18 at 15:58
  • \$\begingroup\$ @PeterSmith - I think if the OP updates the question to match their comment, and better still, quantify "sample the signal as fast as possible", and characterise the signal, then you have the core of its answer: "No it isn't just the charge time for the hold capacitor, ...". \$\endgroup\$ – gbulmer Mar 21 '18 at 18:11

I think the question is about "S/H aperture", or "effective aperture time". Yes, roughly speaking, it is a time required to charge the hold capacitor to the level corresponding to ADC resolution. On fast changing signals it is more complicated.

There is a vast literature on the subject. Please examine, for example, this Texas Instruments application note #223, for comprehensive details and definitions.

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