There are two ways to achieve what you desire. One is a project setting, so will affect the entire design, which may or may not be desirable. The other way is module specific using attributes.
Open the project settings, and navigate to the "Compiler Settings" tab on the left. Click the button for "Advanced Settings (Synthesis)" to open the advanced settings window.
Find the option for "DSP Block Balancing", and select "Logic Elements".
This will completely disable the automatic inferring of DSP blocks, instead forcing all inferred multipliers to be implemented in logic.
The module specific alternative is to use the Verilog
multstyle attribute to inform Quartus that you want to use logic based multipliers. To do this, add the following line directly above the module definition:
(* multstyle = "logic" *)
For example, you might have:
(* multstyle = "logic" *) module someMultipler ( ...
This will tell Quartus to use logic for any multiplier in this module.
You can do the same to request DSP blocks as well, using
(* multstyle = "dsp" *)