Regarding the fairly new High Voltage SiCFET Devices with operating voltages of 1200V+ in leaded TO-247 packages (or variants thereof):

How to isolate the Gate-, Drain- and Source- leads (and heatsink) from each other?

Is maybe isolation between the leads ensured even without additional isolation efforts (assuming no moisture, dirt or dust)?

SiCFET example: SCT50N120

  • 2
    \$\begingroup\$ Your problem is creepage at the PCB and the body of the FET itself. The PCB can be solved by cutouts or moving the drain forward, formning a "tripod". Conformal coating is an option too. \$\endgroup\$
    – winny
    Mar 22 '18 at 15:41
  • \$\begingroup\$ I agree with "Winny" and I have used the same techniques of PCB slots to manage voltage creepage/tracking/spacing and pre-forming the TO-247 to be a tripod. \$\endgroup\$
    – Steve
    Mar 22 '18 at 16:29

1kV is easy, try 30kV but the same techniques are scalable. Insulated thermal conductors are available but these tend to be trade secrets.

Your options for good thermal conduction and electrical insulation of the drain with low capacitance are limited. 3M thermal tape, thin Ceramic wafer, Mica


  • \$\begingroup\$ Looks like a good read Tony, I can't wait to take a look at. \$\endgroup\$
    – Steve
    Mar 22 '18 at 16:34
  • \$\begingroup\$ KEN BAHL (et al) is one of the best PCB suppliers I have had the pleasure to work with. Once at a Vegas trade show he recognized my name from my voice immediately without ever having seen me. \$\endgroup\$ Mar 22 '18 at 17:35

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