Counter/Timer ICs?

Question

EDIT: Just to be clear this is not intended to be a "shopping" question. I am looking for the right technique to construct a very fast counter.

=====

I am looking for a counter/timer IC with the following capabilities:

• > 10MHz max count rate
• ≥ 32 bit depth (preferably >40 bit)
• preferably, a built-in preset or compare function

I will use it to count a succession of events, and give an interrupt when the count reaches a specified value. The interrupt has to occur very fast, before the next event (so less than 100ns), which is why I'm using discrete logic instead of a microcontroller.

Right now I am prototyping with 4-bit counters like the 74LVC161. However I end up having to cascade at least 8 of them, which approaches their propagation delay limits (I calculate a max frequency of 11MHz).

Is there a better solution to this problem? I am willing to try using a CPLD/FPGA to make a huge synchronous counter, but I have no experience and don't know how many gates/logic units are required. What is the best approach?

Answer 1

This can easily be done in an FPGA but I don't think you need anything that complex for what you describe.

• With the 4-bit ICs you already have, you have a terminal count (TC) output. If you feed that to the Count enable input (CEP) of the next counter you synchronize the counters. It should be possible to design a very wide counter.

• To achieve a low and synchronized delay after the event, set the target value that you wish to compare with to the value that occurs 1 cycle before the event occurs, then delay the result 1 cycle with a flip-flop.

To make the comparator simple my own preference is to design a down-counter which is loaded with the target value on (p)reset. When the counter reaches 0 it is done. Optionally add a flip/flop to synchronize the comparator output, and either design the counter to test for 1, or subtract 1 from the preset.

• You can do something similar with the ICs you have. Just choose the preset/load value as ( Max. Counter Value - target period ) then the last TC output will be active for one cycle when you have finished the count.

Just to digress a bit, a shift register is often considered one of the fastest counters you can make since there are no comparators or adders. However, since you need one latch (or flip-flop) per counter value, this is not what you want for a >= 32 bit counter.

Answer 2

A fast processor (e.g. Cortex M3 @ 64MHz) has a ~16ns clock cycle and will respond to an interrupt well within 100ns. Much faster if it has nothing else to do and you just run a 'look at counter value' loop. (You probably need to combine a SW counter as well as a hardware one to have more then 32 bits)

For a very fast >40 bit counter you can use an FPGA. As to how much code/gates you need depends on what action you want to perform. My guess is even the smallest one will suffice.

You will need to learn an HDL language like Verilog and go through the learning curve with the tool set. The tool will also tell you if the design fits in the chosen FPGA. But in the end, if your 'actions' are not too complex, it is very likely to be able to do what you want.

Answer 3

If I understand you correctly (counting pulses and emitting pulse at certain number of pulses) you actually don't need really fast micro controller (20 MHz should be enough) as most support external source for timers clock and chaining multiple timers with last timer outputting directly on output pin.

If this is your case your micro controller will only need to setup registers and enter infinite loop (or sleep), without any need for interrupt or code execution in micro controller.

On newer micro controllers you wont even need to more then one timer as they are usually 32 bit with addition of 16 bit prescaler, which is useful if you want to count numbers multiple of 2^N.

Answer 4

Even a small FPGA will do this with ease. You can get an eval board for Xilinx, Lattice etc. and have at it. Pick and HDL (VHDL and Verilog are the popular ones), and you should be able to download sufficient tools for this project at no cost.

Some CPLDs might be able to do it too, but with an FPGA you probably won't have to worry about resources because you'll not be using much of the available resources.

The combination of an FPGA and processor will solve many problems where one or the other is a poor fit.