How to find power, delay, and area of a synthesized design using Design Compiler?

I have a huge design that is synthesized and mapped to 45nm Nangate library. Is it possible to read the mapped Verilog file in design compiler and find estimates of power, area, and delay without running any optimizations or elaboration in DC? (The original synthesis is done using another tool and I would like to compare its synthesis report with that of design compiler).

The reason I am asking this question is that because the design is so big, DC takes a lot of RAM during elaboration which is beyond the capabilities of my machine. So, I would like to avoid elaboration step and get estimates of power, area, and delay in a simpler way.

• synthesis report ? – Mitu Raj Mar 24 '18 at 19:22
• The circuit is synthesized using another tool. I would like to compare the results with design compiler, but avoid any optimizations – Mahdi Mar 25 '18 at 4:55
• That tool should have produced a synthesis report on the project folder. – Mitu Raj Mar 25 '18 at 4:58
• What I'm looking for is to compare synthesis report of tool X with DC without performing any optimizations or elaboration on the design in DC. – Mahdi Mar 25 '18 at 19:35

Here is not an ideal solution, but I would give a try.

• Read the gate-level Verilog file with -netlist option, so it can be read faster than an RTL file.

read_verilog -netlist my_netlist.v

• Ensure that Design Compiler doesn't optimize the design.

set_dont_touch my_netlist

• Source constraint files if available. If not, define clock(s) at least.

source constraints.sdc

• Compile the design with -only_design_rule option, so that mapping optimizations are not performed.

compile_ultra -only_design_rule

• Then generate the reports.

report_timing
report_area
report_power


P.S. These commands don't form a complete script for synthesis.

• Thanks a lot for your explanation. I will try your solution and will come back with updates soon. – Mahdi Mar 26 '18 at 22:31
• Although I have asserted set_dont_touch, compile_ultra starts mapping the design. Is this the expected behavior? – Mahdi Mar 27 '18 at 20:38
• @Mahdi Actually I don't know what DC does in that case, but I would expect mapping to take a little time even if it is performed. – ahmedus Mar 28 '18 at 12:05
• @Mahdi I modified my answer to certainly disable mapping optimizations. – ahmedus Mar 28 '18 at 13:10
• @CiroSantilli新疆改造中心六四事件法轮功 I rely on STA estimates rather than synthesis. For timing, the accuracy is good at 100MHz clock frequency. Of course, this is not close to the cutting edge. – ahmedus Jul 31 '18 at 9:00