I have a huge design that is synthesized and mapped to 45nm Nangate library. Is it possible to read the mapped Verilog file in design compiler and find estimates of power, area, and delay without running any optimizations or elaboration in DC? (The original synthesis is done using another tool and I would like to compare its synthesis report with that of design compiler).
The reason I am asking this question is that because the design is so big, DC takes a lot of RAM during elaboration which is beyond the capabilities of my machine. So, I would like to avoid elaboration step and get estimates of power, area, and delay in a simpler way.