I'm trying to implement one digit counter from 0 to 9 using an FPGA board. The digit is incremented when the signal "pulse" is set. The "pulse" signal is set every fixed number N of clock cycles. The clock frequency is 5 MHz. However the counter jumps inconsistently depending on the "pulse" period. For example when it's set to 1000000, the counter works fine and the digit is incremented every 1/5 of a second. When the period is different, it does not behave as expected. Even if the period is set longer, every 5000000 clock cycles, it jumps from 0 to 1 to 0..., the increment is 10!
Here's the VHDL code that increments the counter based on the pulse.
process(clk, reset) begin if (reset = '1') then digit_reg <= (others => '0'); elsif rising_edge(clk) then digit_reg <= next_digit; end if; end process; process(pulse, digit_reg) begin if (pulse = '1') then if (digit_reg >= 9) then next_digit <= (others => '0'); else next_digit <= digit_reg + 1; end if; end if; end process;
Any idea what the problem might be?