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Tenting vias is great for:

  • If a via is placed over some silk screen (designator, instruction, warning, etc.) and you want the text to be more readable
  • A compact design with high component density and potential shorts nearby
  • More aesthetic look (solder mask across the board, rather than gold/silver dots everywhere)
  • Stop solder being sucked away during reflow if placed under a component/near a pad

On the contrary, though, I can't seem to find any reason not to tent vias. Assuming you have appropriate test points and the design works 100% (i.e. no need to probe around and check things), is there any reason not to tent every via on the board? Even if you do need to probe, you can still dig through the solder mask and make a connection if worse comes to worse anyway.

Only thing I can think of is increased heat retention if it is a high-current via, but besides that I'm lost.

Any ideas?

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  • \$\begingroup\$ I assume it costs slightly more to manufacture, but I don't actually know that. \$\endgroup\$ – user253751 Mar 26 '18 at 4:42
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    \$\begingroup\$ As long as you're just tenting (not plugging) the vias, there shouldn't be any extra cost. The issue is that soldermask is not very good at bridging gaps, and so the tenting will typically sag or break over the hole. \$\endgroup\$ – Abe Karplus Mar 26 '18 at 4:46
  • \$\begingroup\$ I've seen it claimed that if you tent both sides of the via, then trapped gas could blow out the tenting during reflow. Never seen it as a problem in the real world, though. \$\endgroup\$ – The Photon Mar 26 '18 at 4:55
  • \$\begingroup\$ As @AbeKarplus pointed out, I know first hand there is no cost difference between tented vs untented \$\endgroup\$ – DSWG Mar 26 '18 at 5:08
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    \$\begingroup\$ "Assuming you have appropriate test points and the design works 100% (i.e. no need to probe around and check things)" Well there's your answer right there... [Samsung tented vias in my stove control panel. It made debug and repair miserable, but didn't stop water getting into the vias and eroding them] \$\endgroup\$ – Henry Crun Mar 26 '18 at 5:34
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I use those spots as probe points, and as points where I can solder some botch wires when needed.

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  • \$\begingroup\$ Yeah same, but as I said "Assuming you have appropriate test points and the design works 100% (i.e. no need to probe around and check things)", is there any reason not to tent every via? \$\endgroup\$ – DSWG Mar 26 '18 at 22:51
  • \$\begingroup\$ @STWilliams Prototype board has never enough test points ;) \$\endgroup\$ – Chupacabras Mar 27 '18 at 5:46
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In production, you will often want to test every product to verify it works. Non-tented vias could double as test points for this.

For some crazy edgecases: Tenting vias means you have soldermask on your vias. In some extreme precision circuits this might not be acceptable, since current leakage in solder mask can be an issue (if you look at high-sensitivity measurement devices you often see that the low-current tracks might not have soldermask on them, or at least the guard traces around them isolate the soldermask).

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I tent ALL vias unless I plan to use some of them for probing for the 1st proto pass. Plus, with tented vias you can place them closer to the break-out SM pins without any worry of solder-mask slivers; short traces are also great for keeping the trace inductance low too for de-coupling caps, TVS's and the like. In addition, the less exposed Cu. the better in terms of solder-bridging or under a metallic element of a part. I too have heard about the "volcano" effect but never seen it in real life. There should be no cost adder (to tent vias) either.

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