0
\$\begingroup\$

I am trying to wrap my head around exactly what goes on in an FPGA when I program it, specifically using VHDL. I know all code outside processes run concurrently but what about processes in different vhdl files in the same project? Does the FPGA only run them in the order in which the designer connects their components in the top level entity? Or do they all run concurrently and I have to make sure they are triggered in sequence?

for example I have written three different VHDL files for a CLOCK, A COMPARATOR and a HEXIDECIMAL DISPLAY. (i've omitted a few files for simplicity) I want it so when the clock triggers the comparator, it does its job and then the result is shown on the display, and I have connected them appropriately.

So will all the components run immediately I switch the FPGA on without waiting for its predecessor to do its job? or do they wait till its their turn/they have a signal coming in? I am unsure of whether I should poll the hexadecimal decimal till it sees a signal coming in (input'event) or if that would be unnecessary.

\$\endgroup\$
  • \$\begingroup\$ note: I already know of how LUTs and Flip flops work in an FPGA I'm mostly confused about the order in which things occur. \$\endgroup\$ – D.P Mar 26 '18 at 23:41
  • \$\begingroup\$ It doesn't. The HDL compiler and FPGA logic synthesizer reduce your elegant code to a blindly mechanical set of configurations which makes the design exhibit equivalent logic. For a typical SRAM based FPGA this would only be true once the configuration load process is complete. \$\endgroup\$ – Chris Stratton Mar 26 '18 at 23:51
  • \$\begingroup\$ VHDL describes how you connect digital logic gates and memory elements. All is based on concurrently flowing electrons in wires. So everything is in parallel independent of how many files you need to describe your design. Files (or components) are just a logical unit to help human brains in handling all the concurrency. It's the same with a clock signal. Digital logic (except for FPGAs) could exist without clock, but then your head would explode right for the easiest digital circuits. \$\endgroup\$ – Paebbels Mar 26 '18 at 23:56
  • 2
    \$\begingroup\$ an FPGA without a VHDL program is like an empty breadboard and a box of digital chips .... each VHDL file "plugs" a few chips into the breadboard and connects some of them together .... when all the VHDL files have been processed, then you have a complete circuit \$\endgroup\$ – jsotola Mar 27 '18 at 0:09
  • 1
    \$\begingroup\$ @jsotola, "like an empty breadboard and a box of digital chips", it is a very good analogy. To improve it, I would say it is a breadboard with a bunch of digital chips already inserted, but without any connections. And then along your lines... \$\endgroup\$ – Ale..chenski Mar 27 '18 at 0:52
8
\$\begingroup\$

You have a conceptual difficulty here. VHDL is not a program in the computer program sense, it is a DESCRIPTION how hardware elements are connected. There is no particular order. Once you "program" the VHDL code into FPGA, it creates proper links between logical blocks and configures them.

Once you turn the power on and configuration bits are loaded into all FPGA areas, all FPGA functional blocks work in parallel, all parts. If you need some distinctive sequencing out of your design, it should be done via so-called FINITE STATE MACHINES, which still run in parallel, but change flip-flop states only on certain signal conditions, on clock-by-clock basis, so it looks like it is waiting for some signals and sequentially executes something.

\$\endgroup\$
  • \$\begingroup\$ no need to SHOUT.. \$\endgroup\$ – Mehrdad Mar 27 '18 at 6:13
  • \$\begingroup\$ Thank you, your comment was really helpful! I've used FSM for most of the components in my design now and it is a lot simpler for me \$\endgroup\$ – D.P Apr 4 '18 at 1:52
0
\$\begingroup\$

HDL's connect wires and gates.

If you see a for loop in a descriptor language, its only a macro for connecting sets of wires.

Gates control the flow of information on a bit level, you can choose to AND,OR, NOT and various combinations which can be used to build adders, subtractors, multipliers and what not.

Gates introduce a delay so memory elements (d-flip flops,J/K flip flops) and memory elements are employed to align the information with a clock to prevent metastabilty (from asynchronous switching) and to store information.

HDL's build the gates and memory elements for you on a high level, (similar to the way compilers get paired down to assembly), but this process is called synthesis. HDL's high level code gets synthesized down gates\wires.

Simulate the design before uploading it to the FPGA to make sure you have the right design. Develop testbenches to test the design before synthesizing.

Does the FPGA only run them in the order in which the designer connects their components in the top level entity?

The toplevel of a design means it is the top block in a hierarchical design, you can have sub blocks\archetectures under this block. The toplevel typically connects the GPIO's\ports to your code. The top level is where you connect an external clock to your code (or PLL) and tell which ports to connect to the names of your wires.

Or do they all run concurrently and I have to make sure they are triggered in sequence?

You declare registers and memory elements in conjunction with clocks, a d flip flop can hold information for one clock. A set reset can hold for as long as you tell it to.

So will all the components run immediately I switch the FPGA on without waiting for its predecessor to do its job?

Some FPGA's actually have flash that setup the gates, some are fused and some use different kinds of memory. Some have instantaneous startup times and some take microseconds.

\$\endgroup\$

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.