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I am trying to write a VHDL code that displays an image on a monitor. The purpose is to do some image processing with VHDL. However, I am getting trouble with this segment of code. The image that I am using is small one in terms of resolution. Using a java code that I wrote I took every single pixel's RGB values and pixel locations then RGB values are converted them into binary. That binary data is used to draw image. The problem must be with "when" statements. It says that "this construct is only supported in VHDL 1076-2008". How can I overcome this problem? I am out of ideas.

 IMAGE: process(clk) is
 begin
 if clk'event and clk = '1' then
 vgaData <=  "111111111111" when pos_x = 0 and pos_y = 0 else
 "111111111111" when pos_x = 1 and pos_y = 0 else
 "111111111111" when pos_x = 2 and pos_y = 0 else
 "111111111111" when pos_x = 3 and pos_y = 0 else
 "111111111111" when pos_x = 4 and pos_y = 0 else
 .......
 ....... (goes down and down)
 .......
 "111111111111" when pos_x = 76 and pos_y = 86 else
 "111111111111" when pos_x = 77 and pos_y = 86 else
 "111111111111" when pos_x = 78 and pos_y = 86 else
 "111111111111" when pos_x = 79 and pos_y = 86 ;
 end if;
 end process;
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To answer your question, concurrent assignment (prior to VHDL-2008) is only allowed outside a process. Concurrent assignment takes the form:

target <= expression when condition (optional else)

The equivalent statement inside a process is to use a case statement. This would look like this:

process(inputs) is
begin
  case expression is
    when choice1 =>
      do something;
    when choice2 =>
      do something else;
    when others =>
      do something;
  end case;
end process;

As has been alluded to in another answer, you also need to do something with the output from the statement. If you let us know your wider problem we'd be happy to help.

As an aside, you should also be using the IEEE.Std_logic_1164 package and "if Rising_edge(clk)" statement rather than "clk'event and clk = '1'" for clock edge detection. The latter is a bit old fashioned and is now considered deprecated.

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You are not allowed to use 'when' in that form in a process. Only in assignments outside.
(You can use 'when' with a case statement)

Also that code is rather unusual. How do you want to make an image of let's say 640x480 or 1024x768? You should store your image in a memory and then read it out using x, & y for the address.

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  • \$\begingroup\$ how can I store in memory? \$\endgroup\$ – OnurTR Mar 27 '18 at 6:55
  • \$\begingroup\$ I really need advice. \$\endgroup\$ – OnurTR Mar 27 '18 at 6:56
  • 2
    \$\begingroup\$ @OnurTR, it looks like you've confused two things into one. It sounds like you want a digital logic circuit in an FPGA consisting of (a) a CPU, for processing your display data and storing it in video RAM, and (b) a display circuit, for reading that video RAM data and sending it to a monitor, as the man says above. Furthermore, I don't know if you're confusing what FPGAs and CPUs do. An FPGA is something you design digital logic circuits for, not write computer programs for. \$\endgroup\$ – TonyM Mar 27 '18 at 7:23

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