# Active high, rising edge circuits update state when, exactly?

I'm very new to electrical engineering. On a recent exam, we had a circuit with two JK flip-flops connected in series with one another. The circuit is beside the point, however.

Both flip-flops were active-high and had a delay τ that was one eighth the period of one clock cycle. ( In other words, the time during which the clock was high equaled 4τ. )

Which means the clock cycle was long enough for each flip-flop to update up to four times.

On the exam, the signals to both flip-flops J and K pins were toggled several times while the clock was high, so that--if the flip-flops change state in response to a high signal on the clock--the flip-flops would update state several times before the clock signal fell to zero.

My question is--when someone says a circuit is active high, does the circuit read input to determine it's state only when the clock signal is rising? Or does the circuit respond to changes on its input pins as long as the clock signal is high, regardless of whether the clock signal is rising or constant high?

## 1 Answer

"The circuit is beside the point, however."

Nope. In general, "flip-flop" means an edge-triggered device. If the circuit responds when the clock is at a particular level, it's called a latch.

So a flip-flop (active high) would respond only on the transition from low to high, and will ignore the inputs at any other time.

A latch (active high) will respond to the inputs as long as the clock is high.

To make things worse, given the apparently basic nature of your course, there is the possibility that the two flip-flops form a master-slave flip-flop. This allows you to create an edge-triggered flip-flop from two latches.

So, without actually seeing the circuit, there is no way to answer your question.