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I am amidst writing up calculations for electronics research, but am unsure how to calculate the time delay for the sum output. I am needing to calculate the time-delay for the sum and carry outputs of 1-bit(genus=2) and 2-bit(genus=4) ripple-carry adders. The 1-bit adder has 2 XOR gates, 2 AND gates, and 1 OR gate. The 2-bit adder 4 XOR gates, 4 AND gates, 2 OR gate.

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closed as too broad by Eugene Sh., Finbarr, laptop2d, Michel Keijzers, RoyC Mar 28 '18 at 8:36

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  • \$\begingroup\$ Sum up times on a critical path. \$\endgroup\$ – Eugene Sh. Mar 27 '18 at 15:31
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For a 4-bit ripple carry adder, since the carry is rippled through, the final Cout and S3 is valid only after the propagation delays through each full adder. So the total delay would be: $$t_D = 4 \times t_{FA}$$

Inside Full Adder:

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The critical or most delayed path is for C_out. It is via XOR --> AND --> OR. Suppose all gates have equal delay = \$t_g\$, then \$t_{FA} = 3t_g\$. Therefore \$t_D = 12 t_g \$

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