I have a huge combinational circuit with a large delay. I like to partition this design (based on delay) into smaller parts and later, convert it to a sequential pipelined circuit. Are any of the existing tools, such as Design Compiler, Quartus, Yosys, ABC, etc., capable of such partitioning?
There is a concept called register retiming (or register balancing). Most of the commercial tools have attributes and options for it.
When the option is set, synthesis tool can move registers (flip-flops and latches) forward/backward and tries to optimize timing and/or area.
If it is hard to pipeline a design (e.g. a multiplier) by RTL, all registers can be put consequtively at the inputs or outputs of the design. Fox example, in case 3 registers put at the output, the tool tries to partition the combinational logic into 4 equal parts. I guess, register duplication also should be enabled for better results.
I can give some command examples for Design Compiler. The following command enables retiming in
set_optimize_registers -design My_Multiplier
If timing is the main goal,
-minimum_period_only option can be used.
set_optimize_registers -design My_Multiplier -minimum_period_only
There is also a global option (
-retime), but I don't know whether it can break the functionality of feedback loops.