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I am trying to make a quadrature phase divide-by-6 clock divider circuit in cadence. I managed to complete the circuit and obtained the correct waveform; however, due to some reason I am getting a overshoot of voltage in one of the waveform (see below, 3rd waveform). This is 150mV above 1V.

enter image description here

Can you please suggest methods to correct this?

The circuit design is below: (inv: inverter, by2: divide-by-2 clk divider, by3: divide-by-3 clk divider, ff_prot: D flip-flop)

enter image description here

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    \$\begingroup\$ Match impedances. \$\endgroup\$ Commented Mar 29, 2018 at 0:28
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    \$\begingroup\$ Do you seriously expect us to debug a circuit you haven't shown us? \$\endgroup\$
    – Dave Tweed
    Commented Mar 29, 2018 at 0:45
  • \$\begingroup\$ @DaveTweed Sorry for not providing the circuit. I've added it to the question. I managed to correct some part of it by replacing the latch with a flip-flop (ff_prot, in circuit); but there is still approx 80mV of overshoot. I'm using C2MOS circuit for D-latch design. \$\endgroup\$
    – viliyar
    Commented Mar 29, 2018 at 0:56
  • \$\begingroup\$ How will you analyze reflections without geometry of conductors and dielectric? and /or impedance? \$\endgroup\$ Commented Mar 29, 2018 at 1:18
  • \$\begingroup\$ I just need some insight into what all possible reasons could be for this behavior. I'm not sure I understand which impedance you are indicating to, here. For all the parameters I know, the transistor length and width used are -> PMOS: L=80nm W=4um; NMOS: L=80nm W=2um; Wire width=0.0625um). \$\endgroup\$
    – viliyar
    Commented Mar 29, 2018 at 1:36

2 Answers 2

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If ringing is the culprit, absent rigorous electromagnetic analysis, a simple approach would be to insert series resistances at each gate output and link their value to a variable. Run a few trials varying the resistance from 15 to 150 Ohms. The minimum ringing will likely occur inside that range. If you need to fine tune, the outputs with a higher fan-out will need a lower R value or maybe zero. This is called source termination. The gate output inductance plus the intermediate conductors can interact with the gate input capacitance to cause reflections after the transitions. How to select source termination resistors by looking at signal? Alternately, The waveform in Q2 may have some cross coupling by way of the power supply or ground. A probe on one or both could reveal a need for a lower impedance power supply or grounding net.

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  • \$\begingroup\$ That's a good sugestion but I am not working on the discrete electronics but rather on IC design so introducing resistances would not be a good idea. \$\endgroup\$
    – viliyar
    Commented Mar 31, 2018 at 15:16
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I made some changes to circuit. Suspecting clock delay due to inverters as an issue, first I added two inverters in series on Q2, but it did not help. Moreover it looked very redundant due to 3 inverters in series. So, we took Q4 and inverted it again to get Q2. Surprisingly enough, it fixed the issue. I suspect the problem was during to the switching action of flip flop.

It works fine now. Thank you for help. :)

This is circuit: enter image description here

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