I'm an experienced analog/power designer that's been asked by a coworker to scrub a digital design. He's pretty junior, but a good friend, so I am helping. (So now we're BOTH in trouble. ;-P

We are connecting a LAN9500 and a KSZ8795CLXIC and are hung up on how to wire the MII connection between the two. I realize that there are two MII types: PHY MII and MAC MII. I attached a scrape of our schematic. Our Schemat

I think that this is miswired, with Tx connecting to Tx and all of the handshaking being wrong, too.

But confusion comes from examples like this KSZ8863 Eval board. Where TX connects to Tx and Rx connects to Rx! For this Phy mode example, anyway. Here's what I'm talking about: eval board showing possible contention

Also, does timing between these two chips need to be scrubbed? Or does MII mean that these should connect without glue logic?

Any pointers would be totally appreciated.

Dan (& Brett)

datasheets: http://ww1.microchip.com/downloads/en/DeviceDoc/00002112B.pdf



You need to consider that the data sheets should describe what type of interface is on each device. (i.e. if TX is an output from a particular device or an input). If that is not fully apparent from the data sheet then you should be considering talking to the support folks from the device manufacturers.

I have done designs with RMII both with TX->TX type connection and the crossover TX->RX type connections. It does work.

Another important consideration with MII (and RMII if that is an option that you have to reduce number of inter chip connections) is to carefully consider your reference clock. Ideally you have a clock source that you then route to both devices with equal length routing and very careful attention paid to the signal integrity considerations to keep clocks clean without ringing.

You also want to try to keep the routing of the MII (or RMII) connections with equal length routing for all the signal and control wires.


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