The carry is negated, but when chaining two of those together to a full adder, the negated carries can be combined with a NAND gate to give a normal carry. My questions are now: Does this design have any advantages or disadvantages compared to other ones (e.g. the one Wikipedia shows https://en.wikipedia.org/wiki/Adder_(electronics)) and is it used anywhere (I searched, but couldn't find it)?
It depends on the rest of the circuit you're making. The max length of the signal path still goes through 3 chips, so the speed won't be significantly different to the standard one, but if you had a circuit where you wanted a carry signal that was already inverted then it would be handy.