I'm designing high-voltage enclosure circuitry that engages a lock when either of two HV supplies reach 50V or greater. Both are capable of 6kV output. Below is what I have so far, where R7 represents the lock:
The two similar blocks form comparators against a 5V reference, and Q3 and Q6 form an AND gate. Q9 drives the output.
I've had issues with op-amps and logic ICs burning up with previous designs, so all components are discrete.
This design works well in simulation so far, but I have only yet cranked up the sources to 60V. In reality, a 100:1 resistive divider (10M:100k) will be used to yield a 0-60V range, or thereabouts (200:1 for 0-30V, perhaps).
The issue is that, at 50V, the voltage at the comparator input is too low to overcome Q1's or Q4's \$V_{be}\$. I thought about adding a common-emitter amp with a gain of 10 at the inputs that just saturate a bit above this 50V mark, but that would also require another inverting amp following it.
Is there a simple way to go about this that I'm not thinking of? Or is a change in configuration needed?