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I'm working on a project to sample CAN messages based on a Xilinx Spartan-6 board. I want to get the timing information of CAN messages. The schematic of data acquisition module is shown below.

The module (including AD9226) is working under a clock of 50 MHz.

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Subtracter:

Input from CANH minus input from CANL, to get the differential voltage.

Comparator:

  • If greater than the threshold value, then output dominant ‘0’.
  • If lower than the threshold value, then output recessive ‘1’.

The AD module which I choose is this one which can be directly connected to the FPGA board.

I linked the final output with one I/O pin of FPGA board so I can observe it by a logic analyzer. It looks good when using the logic analyzer.

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But you can notice that there is noise which I don't want.

Here is the result I observed by ChipScope. The sample frequency is 50 MHz.

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There are so many unwanted transitions.

The ADC module is well-designed and can be directly connected to the FPGA, so I don't expect so much noise from the input.

Is there a way I can remove the noise to improve the situation? Is there a design principle I can follow when using an ADC to sample a signal?

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    \$\begingroup\$ why are you using ADC to read a digital signal? \$\endgroup\$
    – jsotola
    Mar 29, 2018 at 20:24
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    \$\begingroup\$ What you're trying to do is perfectly reasonable, effectively making a home-made oscilloscope and they're a popular-enough method for measuring CAN timing. Can I double-check your ADC sample rate. You say 50 MHz - you do mean 50 Msamples/sec and not, e.g., over an SPI interface with a 50 MHz clock? \$\endgroup\$
    – TonyM
    Mar 29, 2018 at 20:29
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    \$\begingroup\$ @Joe. If your going to use an ADC you need to over sample by a factor of 8 or 16 so you can integrate and get clean results. How do you know this is not just Nyquist noise? \$\endgroup\$
    – user105652
    Mar 29, 2018 at 21:36
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    \$\begingroup\$ @Sparky256 Hi, do you mean by averaging of several samples? \$\endgroup\$
    – Joe
    Mar 29, 2018 at 22:28
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    \$\begingroup\$ You can put in Schmitt triggers, they'll do no harm and may help slightly. More importantly though, have you put timing or placement constraints on your firmware design to allow for the reading of a parallel bus at 50 MHz? Otherwise you could be latching in skewed and corrupt data which appears to you as noise. Or are you using someone else's firmware? \$\endgroup\$
    – TonyM
    Mar 29, 2018 at 22:51

1 Answer 1

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Your FPGA has input and output DFFs for each pin. Read up on I/O pin DFFs in Xilinx UG381, particularly on the pin input DFF (ILOGIC2) and the programmable input-pin-to-DFF delay path to that DFF (DDLY).

Use these input DFFs on your ADC input data bus pins to latch in the ADC conversion results.

The timing relationships between a pin to its input DFF and its output DFF are fixed for the silicon, varying only with temperature and slightly from part to part. You can adjust their DDLYs to get a clock-to-setup time that accommodates ADC bus timings.

Then you don't need timing constraints and synthesis routing is eased and consistent over builds. This is much simpler.

Make sure your VHDL takes the ADC bus straight into DFFs, with no combinatorial logic between pins and DFFs. Otherwise, the input pin DFFs can't be used because the circuit can't be routed during synthesis.

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