# Altium Unrouted Net in Fill

I am trying to use vias on a fill to connect copper in Altium, but I keep getting unrouted net constraint errors. I have the following:

The red square and blue rectangle (which extends fully underneath the red square) are fills on the top and bottom layers, respectively. Why would I get an unrouted net constraint here?

• What are the actual errors? – Spehro Pefhany Mar 30 '18 at 0:59
• Un-Routed Net Constraint: Net 5V Between Via (45.2mm,49mm) from Top Layer to Bottom Layer And Via (45.2mm,49.5mm) from Top Layer to Bottom Layer  – Billy Kalfus Mar 30 '18 at 1:04
• I have also tried adding a trace directly between all of the vias, and it did not resolve it. – Billy Kalfus Mar 30 '18 at 1:04
• Are you sure there isn't something funny going on like another via underneath the ones that are showing? Maybe delete the vias and replace them. – Spehro Pefhany Mar 30 '18 at 1:14
• Are you sure you are re-running the design rule check every time you make a change? The DRC error markers will not go away automatically when you fix the error, you need to run the DRC again to get rid of them. – DerStrom8 Mar 30 '18 at 11:25