I have the following two signals A and B
__________ __________
_____| |_________________________________________| |_____
__ __ __ __ __ __ __ __
| |_________________| |__| |__| |__| |__| |__| |________________|
Note that:
- There is no common clock between them available
- Signal B always changes when A is low and A always changes when B is low
I would like to create a 6-bit counter that increments its value every negative edge of signal A and then outputs its value bitwise in between, exactly at the positive edges of signal B.
The problem is I have to share a state between these two, for example:
wire bit_output;
reg [5:0] counter;
reg [5:0] current_value;
always @(posedge signalA) begin
counter <= counter + 1;
current_value <= counter;
end
always @(posedge signalB) begin
current_value <= { current_value[4:0], 1'b0 };
end
assign bit_value = current_value[5];
Now this is unfortunately not a valid Verilog code, for example in Xilinx ISE I get:
Signal current_value[5] in unit test is connected to following multiple drivers:
I tried placing them into one always
statement but this is not possible either:
Assignment under multiple single edges is not supported for synthesis
If I had a common clock I could use a conventional state machine but in this case I only have these two independent signals.
No matter with which solution I come up, I always need to share data somehow.
I do not want to run both paths independently; for example having a counter for SignalB and if it is zero, initialize with data from A because the initial condition would be undefined. I would like to ensure that the data that is spit out on the positive edges of signal B are always properly initialized at the falling edge of signal A even if, for example, only 3 positive signal B edges occur.
What is the easiest way to implement this?
(this is just a simplified example to keep things compact; the actual task is more complicated)