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The specifications required are as follows:
The resistance between ground pins on a connector and the case (chassis) ground should be less than 3 Ohms.
The resistance between any other signal on the connector and case ground should be more than 100 Mega Ohms.
How can I guarantee that my PCB design achieve the two mentioned specs? Isn't there any kind of simulation to this?
I use Mentor Graphics Expedition for PCB design and Hyperlynx for signal integrity analysis.
I'm pretty sure, given the way the specification is worded, that we're talking about two different kinds of ground pins in the connector. The implication is that there are "chassis ground" pins that are connected as directly as possible to the chassis, and that these pins are completely isolated from all of the other pins in the connector, including any "signal ground" or "power return" pins.
Further, this implies that there can be no components connecting signal ground to chassis ground, with the possible exception of a low-leakage capacitor.
In other words, the "active" ground plane of your circuit board (the one that the power and signals are referenced to) must NOT be conencted to the mounting holes (and thereby to the chassis). Only the chassis ground pins in the connector should be connected to the mounting holes, and the copper paths that accomplish this need to have sufficient clearance around them relative to any other copper or components on the board.
You need to consult your PWB laminate supplier and Process Engineer to ensure the solder mask and cleaning process can prevent contamination from affecting this value.
The copper resistance is pretty straight forward with copper weight per area and track width / length tables. However 3 Ω is fairly easy to accomplish with a welded stud, star washers//nuts/crimp lug / contacts + copper tracks. You need to take care about insulators and contact corrosion, but this is much easier than 100 MΩ.
