There are a few things I understand:
- DRAM stores each bit of data to a tiny capacitor with some potential difference.
- Unless the capacitor is connected to low voltage end, the potential difference should remain the same.
Why do we need to refresh the potential difference stored in the capacitor in DRAM?
Why and how does the capacitor lose the charge in DRAM? (Are capacitors connected to low voltage ends?)
Shouldn't the capacitors pertain to the potential difference and DRAM should work like non-volatile memory because of this?
Also if you can answer the point raised by Harry Svensson in comments:
- Why do the capacitors in DRAM need to be updated, yet the capacitors in the gates in analog FPGAs somehow retain their charge?