There are a few things I understand:

  1. DRAM stores each bit of data to a tiny capacitor with some potential difference.
  2. Unless the capacitor is connected to low voltage end, the potential difference should remain the same.

Why do we need to refresh the potential difference stored in the capacitor in DRAM?


Why and how does the capacitor lose the charge in DRAM? (Are capacitors connected to low voltage ends?)

Shouldn't the capacitors pertain to the potential difference and DRAM should work like non-volatile memory because of this?


Also if you can answer the point raised by Harry Svensson in comments:

  • Why do the capacitors in DRAM need to be updated, yet the capacitors in the gates in analog FPGAs somehow retain their charge?
  • 1
    \$\begingroup\$ This question would be much better if it asked why the capacitors in DRAM needs to be updated, yet the capacitors in the gates in analog FPGA's somehow retains their charge. \$\endgroup\$ Mar 31, 2018 at 10:15
  • \$\begingroup\$ @HarrySvensson are the latter similar to flash memory? \$\endgroup\$
    – bobflux
    Mar 31, 2018 at 10:17
  • \$\begingroup\$ @peufeu If I recall correctly, the capacitor (gate) of the NANDs are pulled really high or very low (in V) to force a really strong 1 or a really strong 0. And every time you change the charge in the gate you destroy the gate slightly. In analog FPGAs you set a specific voltage at the gate which makes it behave more like a resistor, imagine an inverting amplifier (op-amp), but instead of resistors, you use two transistors with a specific charge on the gate. - That's how I think it is. I'm no expert though. \$\endgroup\$ Mar 31, 2018 at 10:25
  • \$\begingroup\$ DRAM must be refreshed periodically because capacitor's leakage \$\endgroup\$
    – Long Pham
    Mar 31, 2018 at 12:39
  • 1
    \$\begingroup\$ Unless I'm misreading the question is using the terms volatile and non-volatile backwards...? \$\endgroup\$ Apr 1, 2018 at 4:49

1 Answer 1


In both cases (EEPROM/flash and DRAM) a small (femtofarads) capacitor is used. The difference is the way the capacitor is connected.

In the case of DRAM it is connected to the source or drain of a MOSFET. There is a tiny bit of leakage through the transistor channel and the charge will leak off in a relatively short period of time (seconds or minutes at room temperature). Generally the cells are specified to be refreshed every 64ms, so even at high temperature the data is reliably held. Reading the data is usually destructive so it needs to be re-written after every read.

In the case of a flash or EEPROM cell as used to store configuration data, the capacitor is connected to the gate of a MOSFET. The insulation of the gate/capacitor is very close to perfect and the tiny charge will hold for many years, even at high temperature. The disadvantage is that some method such as quantum tunneling must be used to change the charge on the "floating gate", and that is a much slower process, far too slow to be practical for working memory. Reading is fast and non-destructive, at least in the short term. Using tunneling exposes the gate insulator to a relatively high voltage gradient and exposes failure modes wherein the cell will effectively wear out after a number of writes (typically specified as 10^3 to 10^6 or more).

  • 1
    \$\begingroup\$ This also answers my semi-offtopic question. Great answer! \$\endgroup\$ Mar 31, 2018 at 21:41

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