I am currently doing layouts in CMOS VLSI Design and I have gotten to drawing stick diagrams. The schematic of the 2 input NAND gate is shown below. In drawing the layouts I have trouble deciding between the Source (S) and the drain (D) terminals of the MOSFET. I wanted to ask if these terminals are interchangeable or not. If they are, then are the two layouts shown below functionally identical?
In both designs
They are both "functionally identical".
I believe they are interchangeable. Though your bottom design might need some extra care regarding the output impedance of the two PMOS.
Personally I would prefer your upper design due to it being more symmetric, connection wise.
Just an extra nitpick thing. On your upper design you have the \$F\$ connected to your NMOS on the left side while output is clearly on the right side. It would be better if you connected it on the right side as in your bottom design, as close to the output as possible.
I've designed ASICs at the university I attended to, but it never went further than simulating in Cadence, so I have no professional/expert view on the subject. With that said... the bottom design has lower inductance, it will probably matter in GHz environments. Depending on your design, you might want to also use a Dynamic logic scheme.
The source and drain are interchangeable in cmos logic technologies so your logic is identical in the two examples you have given.
The "bulk" silicon under the transistor is connected to VDD or VSS independently of the transistors.
In this diagram the bulk p substrate is connected to VSS through the p+ region on the left. Now either of the n+ regions can be used as the source. In this example the left hand one is used but it can be changed to the right.