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I am new to Verilog/HDL and I have a problem. Whenever I try to perform an if/else conditional between two registers of different size the synthesis completes but I am never able to get it to fit.

For example: I have an 8-bit register with options. The lower 4 bits are a number between 0 and 15 I need to test against. What is the correct way to do this?

reg [7:0] options;
reg [3:0] conuter;

always @(posedge clk)
begin
    if(conuter >= options[3:0])
        ... do somthing... 
end
    

I have also tried it this way:

reg [7:0] options;
wire [3:0] options_lowerpartof;
assign options_partof = options[3:0];

always @(posedge clk)
begin
    if(conuter >= options_lowerpartof)
        ... do somthing... 
end
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2
  • \$\begingroup\$ These two code samples should synthesize to the same logic (aside from the second having no declaration for conuter). If you had trouble fitting your design, explain more about what your target device was, and why you think this part of the design is what's causing the failure to fit. \$\endgroup\$
    – The Photon
    Commented Apr 2, 2018 at 4:57
  • 5
    \$\begingroup\$ Sorry. Yes they worked I just ran out of space on the device. I should probably delete the question. \$\endgroup\$
    – dave.zap
    Commented Apr 2, 2018 at 7:11

1 Answer 1

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Both the options can help you to compare the part of the register. The main thing which you should keep in mind is that wire are elements in Verilog that are used to connect input and output ports of a module instantiation together with some other element in your design, so it is better to use

wire [3:0] options_lowerpartof; assign options_partof = options[3:0];

only when the only task to be done is the comparison. Here the 'wire' keyword helps to connect two different modules together (this is a concept of modular programming in Verilog).

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