I am new to Verilog/HDL and I have a problem. Whenever I try to perform an if/else conditional between two registers of different size the synthesis completes but I am never able to get it to fit.
For example: I have an 8-bit register with options. The lower 4 bits are a number between 0 and 15 I need to test against. What is the correct way to do this?
reg [7:0] options; reg [3:0] conuter; always @(posedge clk) begin if(conuter >= options[3:0]) ... do somthing... end
I have also tried it this way:
reg [7:0] options; wire [3:0] options_lowerpartof; assign options_partof = options[3:0]; always @(posedge clk) begin if(conuter >= options_lowerpartof) ... do somthing... end
conuter). If you had trouble fitting your design, explain more about what your target device was, and why you think this part of the design is what's causing the failure to fit. \$\endgroup\$