Verilog - arithmetic comparison with part of register

New to Verilog/HDL and have a problem whenever I try to perform an if/else conditional between two registers of different size. Synthesis completes but I am never able to get it to fit.

For example I have an 8 bit register with options. The lower 4 bits is a number between 0 and 15 I need to test against. What is the correct way to do this?

reg [7:0] options;
reg [3:0] conuter;

always @(posedge clk)
begin
if(conuter >= options[3:0])
... do somthing...
end


Have also tried it this way.

reg [7:0] options;
wire [3:0] options_lowerpartof;
assign options_partof = options[3:0];

always @(posedge clk)
begin
if(conuter >= options_lowerpartof)
... do somthing...
end

• These two code samples should synthesize to the same logic (aside from the second having no declaration for conuter). If you had trouble fitting your design, explain more about what your target device was, and why you think this part of the design is what's causing the failure to fit. – The Photon Apr 2 '18 at 4:57
• Sorry. Yes they worked I just ran out of space on the device. I should probably delete the question. – dave.zap Apr 2 '18 at 7:11

wire [3:0] options_lowerpartof; assign options_partof = options[3:0];