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What do the symbols \$GD_{SN}\$ and \$GD_{SI}\$ mean? What is the component’s purpose? The second picture shows its schematic.

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    \$\begingroup\$ Context, context, context. Where did you find it? Post a link to the article. (Put it in your question and not in the comments.) \$\endgroup\$ – Transistor Apr 2 '18 at 12:01
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    \$\begingroup\$ It's improving. Why would you not disclose the part number and give a link to the datasheet? \$\endgroup\$ – Transistor Apr 2 '18 at 12:20
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    \$\begingroup\$ There is no the datasheet,because i see it from the paper in the IEEE \$\endgroup\$ – XM551 Apr 2 '18 at 12:22
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    \$\begingroup\$ Maybe the IEEE paper has a title or URL that you could post. This is like pulling teeth. \$\endgroup\$ – Transistor Apr 2 '18 at 12:26
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    \$\begingroup\$ Title:A 2m BiCMOS Rectifier-Free AC–DC Piezoelectric Energy Harvester-Charger IC \$\endgroup\$ – XM551 Apr 2 '18 at 12:30

What do the symbol ,GDSN and GDSI , mean?

It looks like you have answered your own question. Your second image shows what the three triangles are.

It's simply three cascaded logical inverters with an enable.

The driving force of each logical inverter gets stronger as you go to the right. In other words, the input may be very weak and the output will be very strong.

It's an inverting bufferer.

and what is its purpose?

The triple inverters are driving high capacitive loads, namely the gates of the two MOSFETs. If there wouldn't have been any triple inverter, then it would take too long to charge and discharge the gates of the MOSFETs. So this is clearly a design meant for high speed, or just low power during the time when the MOSFETs are opening/closing.

The gate capacitance of the input to the triple inverter will be considerably smaller than the gate capacitance of the MOSFET pair.

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    \$\begingroup\$ Not so sure it's for speed ... adding stages in series will tend to reduce speed (increasing current gain certainly can, but this looks like an extreme low current design for energy harvesting.). The Vpzt connection on the last stage suggests that level translation may be part of it. \$\endgroup\$ – Brian Drummond Apr 2 '18 at 12:57
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    \$\begingroup\$ (+1) The GD subscript is a strong hint: I guess it means Gate Driver. \$\endgroup\$ – Lorenzo Donati Apr 2 '18 at 13:08
  • \$\begingroup\$ @BrianDrummond Hmm, I'm thinking about how I should edit my question to align with your comment.. but I give up. Your comment is enough. \$\endgroup\$ – Harry Svensson Apr 2 '18 at 13:11
  • \$\begingroup\$ @HarrySvensson I think leave it as is, you're certainly correct that it's driving a high capacity gate. I'm guessing controlled dead time is one of the concerns but I expect it's explained in that paper. \$\endgroup\$ – Brian Drummond Apr 2 '18 at 13:23
  • \$\begingroup\$ The delayed signal Vdly will also have a lower slew rate which can cause issues if not sped up with 3 stages of x10 analog gain per inverter is my reasoning.for Gate drive GD from Gate step charge feeding back to high impedance delay circuit via Miller charge \$\endgroup\$ – Sunnyskyguy EE75 Apr 2 '18 at 13:35

To me looks like a three stage inverting buffer.
But it's not an IEC 60617 standard symbol as far as i know

  • \$\begingroup\$ At least the symbol tells an astute reader it is a Buffered inverter, which implies certain analog behaviour more than std. logic symbols +1 \$\endgroup\$ – Sunnyskyguy EE75 Apr 2 '18 at 13:30

that symbol is called inverter chain

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    \$\begingroup\$ Links to any kind of source? \$\endgroup\$ – Lorenzo Donati Apr 2 '18 at 18:31

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