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QuestiondiagramBook solution

According to the book Vo =0 when VI(gate-voltage) = 0. Why is that so?

Why does the book also assume that both mosfets are operating in the saturation region? when VI = 0.
I appreciate the help. Thanks alot

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  • \$\begingroup\$ Did my answer make sense? \$\endgroup\$ – Sunnyskyguy EE75 Apr 2 '18 at 22:06
  • \$\begingroup\$ no sir, please elaborate more. \$\endgroup\$ – reginald tetteh Apr 2 '18 at 23:26
  • \$\begingroup\$ no , ask what you need to know or better yet, get any CMOS CD4xxx or 74HCxxx inverting gate and test it with 10M R values using 20K output to +5V and 0V instead of +/-2.5V then try using it as an inverting Op Amp with Rin<>Rfeedback for Rf/Rin gain ratio and AC couple to input, then look at any FET with Vgs(sat) e.g.near=2.5V for RdsOn curve \$\endgroup\$ – Sunnyskyguy EE75 Apr 2 '18 at 23:35
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According to the book Vo =0 when VI(gate-voltage) = 0. Why is that so?

Because the two transistors are perfectly matched, \$I_{DP}=I_{DN}\$. So there's no current through the resistor. Which means there's no voltage across the resistor, so \$v_o\$ is at ground potential.

Why does the book also assume that both mosfets are operating in the saturation region?

The condition for saturation of the NMOS device is \$V_{GS} \gt V_{t}\$ and \$V_{DS} \ge V_{GS}-V_t\$.

Since the gate and drain are at the same potential, we know \$V_{DS} = V_{GS}\$ and therefore \$V_{DS}\$ is greater than \$V_{GS}\$ minus some positive value.

The same argument holds for the PMOS device with appropriate sign changes.

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  • \$\begingroup\$ Would IDP=IDN if the transistors were not perfectly matched? \$\endgroup\$ – reginald tetteh Apr 2 '18 at 23:24
  • \$\begingroup\$ @reginaldtetteh, no, they wouldn't, and it is not a reasonable assumption for a real circuit to have perfectly matched NMOS and PMOS. But that's the assumption your book used to get the conclusion that the output is at 0 V. \$\endgroup\$ – The Photon Apr 3 '18 at 0:12
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When the Vgs =|Vt| for both Nch and Pch you have total (Vdd-Vss)/2 as the input output bias =0 which could be proven with a 10M feedback resistor.

Under this condition when Vgs =Vgs(sat)=Vt it means the threshold of saturation which shunts the supply at some specified xxx uA current. This is adjusted in CMOS to give RdsOn a slightly higher value during transition than when full Vdd or Vss is applied to Vgs. Each max voltage rating has a Standard output Ron and the VTech must be selected to make good signal integrity driving capacitive gate loads at high speed.

But in this question it would operating in the linear mode with greater current consumption than static logic levels . As such original CD4xxx series logic was often used with hex inverters as 6 negative feedback op amps with high GBW product using Rf/Rin=10 for single stage and up to 1000 for buffered 3 stage CMOS .

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