I am trying to understand how to select an appropriate MOSFET driver for controlling a DC motor. I went through quite a lot of literature from Texas Instruments and Microchip, but I am still not able to completely understand how to exactly calculate the gate driver current. Microchip has an application note on how to calculate the gate drive current which notes that the gate drive current (I_G) = Q_G/t, where Q_G is the total gate charge and t is the rise time.

While looking at some drivers on the TI website, I found the DRV8701 and the corresponding EVM module. Going through the schematic the GH and GL pins are connected through a 0 Ohm resistor to the gate of the transistors CSD18532Q5B. The maximum series gate resistance of MOSFET is 2.4 Ohm. According to the DRV8701 datasheet, I_DRIVE is 6 mA when the R_IDRIVE is <1KOhm to the ground ( I am assuming this the R_IDRIVE I should be looking at ). When I do the math for required Gate current as per the Microchip Application note, it comes out to be 8.05 A (=58 nC/7.2 ns). Even if I look at the maximum I_DRIVE current of the DRV8701 (150 mA), this requirement will not be satisfied.

I am not sure what I am doing wrong. When I use a PWM signal does the I_G value reduce depending on the duty cycle? Is this why the 8701EVM is capable of driving the said FET

  • \$\begingroup\$ Sad to say, but \$58\:\text{nC}\$ in \$7.2\:\text{ns}\$ is indeed actually about \$8\:\text{A}\$ for that short moment in time. You will need to drop a rather large hammer on that gate. That hammer will probably be pulling charge off of another capacitor somewhere. \$\endgroup\$
    – jonk
    Apr 3, 2018 at 0:28

1 Answer 1


For LARGE gate_driver ICs, there will be package/bondwire/PCB/VIA/bypass_cap inductance and onchip well-substrate capacitance that will resonate in the 20MHz to 10MHz region. To attempt a 7nanosecond gate-drive event does not buy you any enhanced performance nor any improved reliability.

The various gate-driver ICs will have resistances in the well-substrate capacitances, thus self-dampening..... maybe.

The appropriate Rdampen is sqrt( L / C) = sqrt(10nH / 10nF) = sqrt(1) = 1 ohm.

Given the bulk silicon has resistance, the onchip losses probably are 1 ohm.

You just need to have the external Cbypass (0.1uF?) within 1cm of the Gate Driver IC and Use a GND plane under the IC, Vin, Vout, VDD connections.

Using a Ground Plane will reduce the inductance of that 10mm PCB trace by 5:1 or 10:1, but you still have the bypass_cap inductance, any PCB via inductance, IC leadframe and bond wire.

To predict behavior of this MECHANICAL setup, you must include Inductance of VDD path and GND path, or VDD and Vout (for charging the FET gate), or GND and Vout (for discharging the FET gate). Thus I cheerfully approximate the inductances of those 3 paths as 10 nanoHenries. Achieving speed in switching requires excellent thinking about how to minimize energy stored in all the conductive structures. Knowing the difficulties of this, I use 10nanoHenry to model each of the 3 paths: VDD_to_GND, VDD_to_Load, GND_to_Load.

As your chosen IC attempts to provide that 8 amps, the surge in current ----- 8 amps in 8 nanoseconds, through 10nH, will cause this voltage across the 10nH

V = L* dI/dT

V = 10nH * 8 / 8nS = 10*8/8 * NH/nS = 10 volts.

Thus your 15 volt supply will abruptly sag (inside the IC) by at least 10 volts, and maybe more, because the Vout lead also will be 10nH and a similar voltage upset will occur there.

Thus unless you get the inductances DOWN to 1 or 2 nanoHenry (including internal gold-bond-wire inductances) in VDD and RTN and Vout pins on the package, your edge rate will be 20 nanoseconds or so. Partly because the inductances prevent faster output edges.

The silicon processes used likely are old-time CMOS 15volt logic processes ---that is, 15volt NAND and 15volt FlipFlip devices ---- with 2/3/4 nanosecond delay per raw internal inverter. The demand of LARGE output currents is what upsets the VDD and GND (possibly causing oscillation) and causes large voltage drops across VDD/GND/Vout package pins (and the PCB conductive structures).

The Vin pin, with 10 or 20 pF, draws only small charging currents ---- 10pF charging 10 volts in 10nanoseconds, using I = C * dV/dT, ---- such as 10milliAmps.

  • \$\begingroup\$ I am not quite sure if I followed this answer completely, but what you are saying is that if there's a bypass capacitor across VDD and ground, the driver IC will be able to still supply the required 8A current but the IC will also see a sudden voltage drop of about 10 V. Also the PCB layout will determine the actual rise time. Is this correct? \$\endgroup\$
    – acexa616
    Apr 3, 2018 at 16:40
  • \$\begingroup\$ The inductances will have large voltage drops for the first few nanoseconds, as the current attempts to rapidly change. The VDD--GND voltage across the IC will sag, drop, to something rather low, perhaps 5 or 6 or 8 or 10 volts, causing the PEAK current to drop during those first nanoseconds. Once the VDD/GND/Vout pin inductances have built up the needed current, THEN you will have the available current. This formula: I = 1/L * integral(VdT) can be used and substituting:1/10nH *( 10v_VDD * 10 nanoSec), we learn after 10nS the current may have risen to 10 amps, *if the IC is capable. \$\endgroup\$ Apr 4, 2018 at 3:20
  • \$\begingroup\$ Assume you have 5nH in the VDD pin. And the IC switches from 0 current to 8 amps in 8 nanoseconds. The voltage drop across VDD pin (PCB inductance, any PCB vias, the VDD bypass cap likely 3-5nH, the PCB trace inductances and whether over planes or over air, the IC package/leadframe inductance, the bondwire inductance, the onchip metallization inductance) at 5nH will be V = L * dI/dT and the dI/dT will be greater than 8amp/8nS because of start-to-rise and start-to-level-off regions. So assume 8amp/6nS and 5nH; you'll see 1.333 * 5 = 6.6 volts drop across the VDD pin. And same when go low. \$\endgroup\$ May 3, 2018 at 5:09

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