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I need to create a VIA stitching on my design but the option doesn't work:

I select the width of my VIA, the area where I want to place all of them, and the net to be connected.

At the end it displayed:

Unable to add any stitching vias to net GND_3

(GND_3 is the name of my ground plane)

I have 10 layers on my board. No tracks are passing under my area, and no components are placed.

note: It was working when no tracks were routed. So maybe the option has no place for the vias...

enter image description here

enter image description here

Thanks for reading and maybe helping.

EDIT 04.04.18: The placment of the vias stitching is placed on the design but there are no via on it (always the same message "unable to add stitching via"). I have like 20 vias stitching area but with no via. enter image description here Altium version: 1,0,11 (build 97) Altium NEXUS

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  • \$\begingroup\$ Check your via sizes and clearance rules and make sure the rules aren't preventing the vias from fitting \$\endgroup\$
    – DerStrom8
    Apr 3, 2018 at 11:01
  • \$\begingroup\$ Thanks for your answer, i have two rules for the via (power and all). In this case the GND should be minimum 0,5mm for the hole and 1 mm for diameter. Concerning the clearance (of component), it is 0,254 mm. I tried with this parameter as input for the vias stitching but same results \$\endgroup\$
    – JordanM67
    Apr 3, 2018 at 12:29
  • \$\begingroup\$ Isn't 2018 still in beta? I'd stick with 2017 \$\endgroup\$
    – Voltage Spike ♦
    Apr 3, 2018 at 15:55
  • \$\begingroup\$ It was released just after Christmas IIRC. AD18 is what you get on altium.com, at least \$\endgroup\$
    – MrGerber
    Apr 3, 2018 at 16:27
  • \$\begingroup\$ At the moment, I am using Altium Nexus, do you think Altium Nexus doesn't support vias stitching ? \$\endgroup\$
    – JordanM67
    Apr 4, 2018 at 8:10

2 Answers 2

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This happened to me and I finally figured it out! I had 3 GND planes I was looking to stitch and the via stitching tool would give me the same message. I had to shelve the larger polygons I had for power on an inner layer before the feature worked. Hope this helps for future reference.

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    \$\begingroup\$ Worked for me. I had to shelve every polygon that wasn't the GND net I was trying to stitch and then it worked. \$\endgroup\$
    – Shredder
    May 27, 2021 at 20:03
  • \$\begingroup\$ +1 shelved other polygon and reshelved \$\endgroup\$
    – Electronx
    Sep 2 at 20:40
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I believe via stitching is only possible if you have the GND_3 plane on multiple layers. So if you are trying to stitch GND_3 you have to make sure the underlaying layer is also GND_3

Edit: as read in Altium Via stitching vs Via Shielding

Via stitching is meant to connect a signal on one layer with the same signal on another layer. Think of connecting a VCC polygon pour on top with a corresponding power plane. The vias generated for this kind of connection are meant to be evenly distributed over an area (which can be along a line, but doesn't have to be)

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  • \$\begingroup\$ I have several ground on my board main are GND 2 and GND 3. This two ground are seperate by a galvanic isolation. On my 10 layers stack, I also have ground_optocoupler but the top layers and bottom layers are covered with GND 3 \$\endgroup\$
    – JordanM67
    Apr 3, 2018 at 15:29
  • \$\begingroup\$ I suspect you also can NOT have another plane of another net intersecting with any part of the stitched area. \$\endgroup\$
    – Techydude
    Apr 3, 2018 at 15:35
  • \$\begingroup\$ That means if you have more than 2 layers, you cant use the via stitching ? strange no ? my layer stack is (top signal (with ground plane) - gnd_opto - vcc - gnd_3 - signal - gnd_3 - signal - signal - gnd_3 - bottom (with ground plane GND_3) \$\endgroup\$
    – JordanM67
    Apr 3, 2018 at 15:42
  • \$\begingroup\$ Yes you can use via stitching with more than 2 layers, but you need to use different via's, you can't use the regular through hole via's if you just want to connect two inner layers, you need buried via's. Altium automatically selected buried vias when two inner planes are selected in the drill pair option. Try editing the drill pair option it specifies the layers that the via's starts and ends on. Altium Documentation:altium.com/documentation/18.0/display/ADES/… \$\endgroup\$
    – Remco Vink
    Apr 4, 2018 at 6:53

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