Design a circuit from logic gates, flip flops and/or multiplexers

Question

I would like to create a simple circuit from logic gates, flip-flops (no RLC components) to do the following task:

This circuit has 5 inputs (4 positive real-valued signals \$x_1, x_2, x_3, x_4\$ and a clock signal \$clk\$). The output signals \$y_1, y_2, y_3, y_4\$ are determined as follows:

At the rising edge of \$clk\$, the output signal \$y_i\$ with \$i =1,4\$ correspoing maximum input \$x_i\$ with \$x_i = max(x_1,x_2,x_3,x_4)\$ at this time will have value \$1\$ while other output signals are zero during that period.

For example, \$x_3 = max(x_1,x_2,x_3,x_4)\$ then \$y_3 =1\$ and \$y_1 = y_2=y_4=0\$.

Because I don't know how to do starting from logic gates, I tried to write verilog code and then synthesized it to get the circuit. However, I think the result is too much complicated than necessary. Components such as logic gates, flip-flops, multiplexers are OK but the comparator block is maybe too complex. Is there a simple circuit to do this task? It can be obtained from circuit design from logic gates or synthesized from verilog.

Input signals \$x_1, x_2, x_3, x_4\$ are positive real-valued signals but I don't need high precision, only about 3 significant figures are OK.

Below is my code and the circuit obtained from this code.

module example (clk, x1, x2, x3, x4, y1, y2, y3, y4);
input clk, x1, x2, x3, x4;
output reg y1, y2, y3, y4;

always @(posedge clk)
    if((x1>x2) && (x1>x3) && (x1>x4))
        begin 
            y1 <= 1'b1;
            y2 <= 1'b0;
            y3 <= 1'b0;
                y4 <= 1'b0;
        end
    else if((x2>x1) && (x2>x3) && (x2>x4)) 
        begin 
            y1 <= 1'b0;
            y2 <= 1'b1;
            y3 <= 1'b0;
            y4 <= 1'b0;
     end
    else if((x3>x1) && (x3>x2) && (x3>x4))
        begin
            y1 <= 1'b0;
            y2 <= 1'b0;
            y3 <= 1'b1;
                            y4 <= 1'b0;
        end
     else if((x4>x1) && (x4>x2) && (x4>x3))

        begin
            y1 <= 1'b0;
            y2 <= 1'b0;
            y3 <= 1'b0;
        y4 <= 1'b1;
        end
   endmodule

Schematic obtained from the code above:

Answer 1

• The verilog code you write for FPGAs deals with digital logic. It just sees signals either has a "high" or "low", It does not know any values in between. In your current code you are just comparing between signals on the basis of high and lows. You are interested in "real values", say an analog signal which varies between 0 to 5V, and you want to compare them. What you need is only a set of analog comparators. For example for two signals:

• Another way is to plug your analog inputs to ADCs, convert it into digital equivalents. Say for example 10-bit digital values. And feed these digital values to your FPGA. You would need to write a similar verilog code for comparison of these signal vectors and drive outputs accordingly.

Answer 2

One way to simplify the circuit is to replace the last else if by a else as you should always specify the output of your function for any input. After that, you could always try to create the logic table by hand and see if you can find a pattern, but my personal opinion is that you should probably use a FPGA or microcontroller for that.