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I have recently purchased SST25VF080B SPI Flash

SST25VF080B SPI Flash Datasheet

I have downloaded the software driver (written in C?)

SST25VF080B Software Driver

Since I want to use it with a Parallax Propeller MCU I will convert/port the driver to the SPIN language.

What I want to ask is; How do I wire the HOLD and WP pins so that those functions are NOT available?

These are the notes from the datasheet:

4.1 Hold Operation The HOLD# pin is used to pause a serial sequence underway with the SPI flash memory without resetting the clocking sequence. To activate the HOLD# mode, CE# must be in active low state. The HOLD# mode begins when the SCK active low state coincides with the falling edge of the HOLD# signal. The HOLD mode ends when the HOLD# signal’s rising edge coincides with the SCK active low state. If the falling edge of the HOLD# signal does not coincide with the SCK active low state, then the device enters Hold mode when the SCK next reaches the active low state. Similarly, if the rising edge of the HOLD# signal does not coincide with the SCK active low state, then the device exits in Hold mode when the SCK next reaches the active low state. See Figure 4-2 for Hold Condition waveform. Once the device enters Hold mode, SO will be in highimpedance state while SI and SCK can be VIL or VIH. If CE# is driven active high during a Hold condition, it resets the internal logic of the device. As long as HOLD# signal is low, the memory remains in the Hold condition. To resume communication with the device, HOLD# must be driven active high, and CE# must be driven active low. See Figure 5-3 for Hold timing.

4.2 Write Protection SST25VF080B provides software Write protection. The Write Protect pin (WP#) enables or disables the lockdown function of the status register. The Block-Protection bits (BP3, BP2, BP1, BP0, and BPL) in the status register provide Write protection to the memory array and the status register. See Table 4-3 for the Block-Protection description. 4.2.1 WRITE PROTECT PIN (WP#) The Write Protect (WP#) pin enables the lock-down function of the BPL bit (bit 7) in the status register. When WP# is driven low, the execution of the Write- Status-Register (WRSR) instruction is determined by the value of the BPL bit (see Table 4-1). When WP# is high, the lock-down function of the BPL bit is disabled.

So the WP Pin I take it has to be tied high? So I would wire a 10K resistor from the +3.3V supply to the WP Pin But how I secure the HOLD Pin?

Thank You for reading.

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The trailing "#" on the names of WP# and HOLD# is an indicator that they are active-low signals -- their functions are activated when they are driven low. They are both inactive when driven high, and this is borne out in their descriptions:

As long as HOLD# signal is low, the memory remains in the Hold condition. To resume communication with the device, HOLD# must be driven active high…

and

When WP# is high, the lock-down function of the BPL bit is disabled.

Pull both signals high with 1KΩ (or any similar value you have available) resistors. 10KΩ is a bit more than I'd feel comfortable with.

You could also tie the signals directly to VCC, but using pullup resistors makes it possible to pull the signals low later if needed.

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