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I have finished writing a project with separate VHDL files. Most of the components have connections directly to the FPGA ( which I have instantiated and connected in the top level file) but a few do not. to connect these "internal" components appropriately can I instantiate them in the top level file and connect them only to signals?(like one would in a test bench) or do I have to instantiate each entity where needed in different low level vhd files?

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Anything you can put in the other files you can also put in the top level file.

So there is no reason you can't instantiate any components/entities you want in the top level.

Note that the synthesizer will trim out any logic that doesn't somehow connect to a port. Because if it doesn't touch a port then it doesn't do anything in the real world. Note that the connection to the port may be via intermediate signals, through other components, or through other logic. It doesn't matter, so long as it somehow connects.

You can certainly connect an instantiated component only to internal signals. As long as those signals go somewhere else also.

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  • \$\begingroup\$ I'd like to add: if you are able to instantiate everything in the top level, you should. Simply because you can, you already prove that the modules don't need internal signals of other components and are therefore categorically not submodules. Don't add levels of hierarchy just for the sake of hierarchy. \$\endgroup\$ – DonFusili Apr 4 '18 at 5:34
  • \$\begingroup\$ Thank you for your answers! I was also thinking the same thing but all the examples I had on hand always had at least one port on a component connected to one port of the entity, and I couldn't find anything specific to this online. \$\endgroup\$ – D.P Apr 4 '18 at 13:51

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