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I am programming a mbed LPC1768 for a constant current discharger. I plan to use the DAC output on the LPC1768 for setting the current in my discharge circuit.

edit: The trouble i am having is related to the voltage from the DAC during start and reset. I already made and tested the discharge circuit and it's NOT connected at the moment. At the moment i only have Rpulldown connected on the DAC and am viewing the DAC output on my scope.

schematic

simulate this circuit – Schematic created using CircuitLab

I noticed that under start and reset the uC DAC goes to around 2V for a very short time. I guess it goes to some state untill i define the output in my code, but im not sure of it. edit: how do people usually deal with this kind of problem?

In my circuit these 2V is equal to 20A of discharge current. I dont want this to happen!

I tried pulling the DAC down with a 1K resistor and it sure clamps the DAC on start (goes to around 50mV on reset), but it also pulls the analog voltage down from what its set at in my code. Also tried 12K but that was not enough to clamp the DAC.

I have some different solutions to this problem, but they all involve transistors or relays. I was thinking there must be a more elegant way to deal with a problem like this and i can't be the first to have such a problem.

Can you guys please give me some tips on how to solve this problem? Should the DAC behave like this or am i doing something wrong?

Many thanks in advance!

Edit: added schematic, cleared up some confusing text.

Edit: This is how i am currently dealing with this problem. Any problems doing it like this or is it acceptable? It works but to me it seems a bit like a cowboy solution :)

Base is held high by a pullup resistor and this closes the relay loading the DAC output with 1K and pulling it to gnd. When enable is pulled low in my code the relay opens ands the DAC funtions as supposed.

enter image description here

edit: some code i tried running. just cycles the DAC between 0 and 3.3V. When i push / hold the reset button the DAC exhibits the behavior im talking about.

#include "mbed.h"

AnalogOut out(p18);


int main()
{
    out = 0;
    while(1) 
    {
    out = 1;
    wait(1);
    out=0;
    wait(1);
    }
}

edit: added scope capture of glitch.

Only DAC output on start, no load attached:

Only DAC output on start, no load attached

With 10K across DAC:

With 10K across DAC

With 1K across DAC:

With 1K across DAC

1K across DAC, running a program that should toggle DAC between 0-3.3V. Goes to 3.3 with no / lighter load:

1K across DAC, running a program that should toggle DAC between 0-3.3V. Goes to 3.3 with no / lighter load.

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  • \$\begingroup\$ What DAC are you using? \$\endgroup\$ – Billy Kalfus Apr 4 '18 at 14:13
  • \$\begingroup\$ Welcome to the site. Please can you edit your question to show a schematic (not a block diagram). The schematic editor here is a breeze to use. The better the quality of question, the better the quality of the answers you will attract. Again, a warm welcome to the site. \$\endgroup\$ – TonyM Apr 4 '18 at 14:13
  • \$\begingroup\$ @BillyKalfus, I imagine it's the DAC in the LPC1768 but the post isn't clear. The circuit of the current regulator it drives is a mystery, too. Hopefully, OP will clear all this up by posting a schematic shortly. \$\endgroup\$ – TonyM Apr 4 '18 at 14:15
  • \$\begingroup\$ The schematic is to be useful to the readers rather than yourself. Otherwise, people have to piece it together in their heads. The better the quality of question, the better the quality of the answers you will attract. \$\endgroup\$ – TonyM Apr 4 '18 at 14:43
  • \$\begingroup\$ Which DAC output pin? Does it have any alternate functions which might be active at boot? Show the code you use to configure it for use as a DAC. \$\endgroup\$ – Chris Stratton Apr 4 '18 at 15:58
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During a reset, such as on power-up, your LPC1768 I/O ports will be configured as GPIOs in input mode. An LPC1768 I/O pin can output up to 3 uA of leakage current in this mode. When configured as a DAC, the same pin is specified as capable of driving a load resistance of 1 K or higher.

You don't specify your op-amp so let's assume that has an input leakage current of 2 uA. (You can readily find alternative op-amps with much less input leakage than this if yours is higher.)

This leakage current will be conducted to 0 V by your pull-down resistor and will produce a voltage drop across it, following V = IR. This voltage will drive your op-amp input during reset, until your software has configured your I/O for DAC operation, so the resistor voltage drop needs to be acceptably low. However, the resistor value should ideally be well above 1 K.

As an example, let's consider a resistor voltage of 20 mV. This corresponds to your op-amp driving 2 mA through your current regulator, assuming perfect accuracy there.

Then R = V/I = .02/0.000005 = 4000 ohms (a 3K9 resistor).

After reset, your software should configure the DAC while leaving the I/O pin in its initial state, as a GPIO input. Once the DAC is in the correct mode and set to zero, the GPIO can be configured as a DAC output. The I/O pin's optional pull-up resistor must not be used.

FURTHER FINDINGS...

From the LPC1768 user manual (UM10360), I didn't think the I/O pin pull-ups are enabled after reset. However, @Dorian has found information in the errata that states that they are.

Therefore, instead of the above, you can use an external defeat circuit to clamp the op-amp input to 0 V until the LPC1768 is stable and ready to drive its ADC output.

Choose a suitable logic-level FET for Q1 that is ON with a Vgs of 3 V or ideally down to Vgs of 2.7 V.

schematic

simulate this circuit – Schematic created using CircuitLab

On power-up, GPIO will be internally pulled high but it also pulled high by R2, which is added for certainty after the errata affair. Q2 will conduct and short R1 to deck, ensuring that the op-amp input is zero. Once your software is up and running, it first configures GPIO/DAC to be a DAC driving 0 V. It can then configure GPIO to be an output driving low, turning off Q2 and allowing the op-amp circuit to work normally.

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  • \$\begingroup\$ I will look more into this tommorow.You may be on to something \$\endgroup\$ – Swagministeren Apr 4 '18 at 19:34
  • \$\begingroup\$ Do i get this right? During startup i have to deal with 3uA of current and this should develop some voltage over the pulldown resistor? If i load the DAC with 1K i get 50mV. Should it not be 3u * 1K = 3mV. \$\endgroup\$ – Swagministeren Apr 5 '18 at 13:11
  • \$\begingroup\$ @Swagministeren, you're ignoring the leakage from your op-amp, plus the behaviour of your software - have another read of it. \$\endgroup\$ – TonyM Apr 5 '18 at 13:20
  • \$\begingroup\$ The opamp is not connected yet \$\endgroup\$ – Swagministeren Apr 5 '18 at 13:29
  • \$\begingroup\$ What i don't understand is. How can it be related to my code? It's happening during resets, i don't think my code is being executed in that time... \$\endgroup\$ – Swagministeren Apr 5 '18 at 13:31
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The schematic below takes advantage of the fact that a JFET with gate tied to source is a low impedance. If you make sure that the ENABLE is not taken high until your DAC output is stable, then the MOSFET will be held off because the input to the amplifier will be held close to 0V.

Update to address comment: A JFET with gate tied to source (even through a resistor) is a low impedance when unpowered (effectively), so the circuit starts up with a low impedance at amplifier input.

When you take ENABLE high, the JFET becomes a high impedance and is effectively out of circuit.

schematic

simulate this circuit – Schematic created using CircuitLab

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  • \$\begingroup\$ Yes something like that i also had in my mind if everything else fails :) thanks \$\endgroup\$ – Swagministeren Apr 4 '18 at 19:36
  • \$\begingroup\$ Can you tell me your reasoning for a JFET instead of a BJT or something similair? \$\endgroup\$ – Swagministeren Apr 5 '18 at 13:15
  • \$\begingroup\$ @Swagministeren It must conduct when there is 0V on the gate. \$\endgroup\$ – Jeroen3 Apr 5 '18 at 13:56
  • \$\begingroup\$ J1 is not closed at ENABLE = 3.3V. \$\endgroup\$ – Dorian Apr 10 '18 at 12:23
  • \$\begingroup\$ I apologise for the short comment without explanations. See the comment on Tony solution for details. \$\endgroup\$ – Dorian Apr 10 '18 at 18:23
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"If everything else fails then read the datasheet" and the errata to I might add. See the errata sheet for LPC1768 page 19: "The General Purpose I/O (GPIO) pins have configurable pull-up/pull-down resistors where the pins are pulled up to the VDD level by default. During power-up, an unexpected glitch (low pulse) could occur on the port pins as the VDD supply ramps up."

They mean the internal pull-up resistors of ~100k which is consistent with your observations: 50 mV for 1K pull down resistor and I just can guess a ~500 mV for 10K resistor.

Bad chip design I might say.

What to do ?

  1. One option is based on the assumption that all I/O are behaving in the same way and use a transistor like in Peter Smith solution. Still, this is subject to hazard If I understand well the meaning of "could occur". Shorter glitches still "could occur"
  2. A second option if you don't need quick variations on Iout is to place an RC filter to smooth the glitch like this:

    schematic

simulate this circuit – Schematic created using CircuitLab

With these values, 10 ms startup time, the glitch will be less than
50mV. R1 is there just as protection for an accidental digital
output setting for the pin.

3. A third option related to Peter Smith solution is to use an OA with shutdown input like OPA211

In any solution you choose it's a good practice to limit by hardware the damages that can by done by software errors and here I can suggest two options:

  1. Place a power resistor on the mosfet drain. Let's say your lowest battery voltage is 5V maximum 10V and the maximum current is 4A then place a 1 ohm resistor, the current will newer go above 10A no matter you do with the DAC output or enable output. I strongly recommend you to use that for the development stage.
  2. Set the DAC reference as high as possible and use the maximum range available as so the max DAC output will be as close as possible to the voltage that can be accidentally applied then use a resistive divider to bring the voltage in the range you need.

Let's say the max DAC output is now 0.5V for 5A max output. If by mistake the DAC output goes to 5V you will have 50A at least R1 will burn in flames.

If the max DAC output would be 3V, divided with a 6:1 resistor divider to 0.5V then an accidental 5V applied on DAC output will output only 5*5/3 ~8A , not a disaster, you have time to take action before something burns. In addition the startup glitch is also is divided six times.

schematic

simulate this circuit

Resistor values are not critical you can make some adjustments in software

Bonus: how to make a micro-controller design flaw even worse than it is.

You might think that you power on the board, change the pin to DAC and ready! How much time this can take on a processor that can run at 100MHZ? Microseconds? Wrong answer. I don't had time to read the all LPC1768 documentation but here is the worst nightmare that happened to me:

  • Power on, your DAC output is already high, wait for reset release some ms.
  • The microcontroller starts with the low power 32 khz clock
  • It runs the compiler generated code to initialize the variables and arrays if you not specifically told him not to do so. At 32 kHz clock it might take a loooong time.
  • Finally you get the control, change the system clock to high speed, wait for change. It might take some ms to.
  • Now you change the DAC output. Hundreds of milliseconds have passed with tens of amps running through your battery.

LATER EDIT after simulating both Tony's and Peter's solutions , they both share the same flaw, the transistor switch off/on voltage is over 4V shows the simulations. On a 3.3V Tony's solution doesn't cut the spike at all and Peter's solution is still pulling the DAC output. Which leaves the improved Swagministeren's solution the best that cuts DAC output to some mV on power on and switch off completely after putting enable to zero.

schematic

simulate this circuit

The simulation DC sweep shows large margins for release and cut for ENABLE over 2V the spike is less than 10 mV, for ENABLE under 500mV the DAC output is completely released.

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  • 1
    \$\begingroup\$ I really don't understand the down vote, the solution is simple, it does not require other I/O pins, it has hardware limit for the maximum current which makes-it software error proof. \$\endgroup\$ – Dorian Apr 4 '18 at 18:29
  • \$\begingroup\$ i already tried that. i already said that \$\endgroup\$ – Swagministeren Apr 4 '18 at 19:30
  • \$\begingroup\$ Sorry, I missed that, It was there from the beginning? The spike is still 2V with 12k? \$\endgroup\$ – Dorian Apr 4 '18 at 20:03
  • \$\begingroup\$ If we assume a DAC reference of 5V you are right that it would correspond to 50mV with a 1K resistor, but the reference for the DAC is 3.3V so i should get 33mV, should i not? If i put a 12K on its not enough to clamp the voltage. If i put in 1K it clamps the glitch to 50mV but it also pulls down the DAC once its configured so it will read out less than i tell it to in software. \$\endgroup\$ – Swagministeren Apr 5 '18 at 13:04
  • \$\begingroup\$ If i put in an RC circuit like you described it dampens the glitch on first power up, but the capacitor stays charged when i cut the power supply for the mbed. \$\endgroup\$ – Swagministeren Apr 5 '18 at 13:14

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