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I am doing simulation of my research design on single FPGA, in which I simulated two switching chips ASIC and an FPGA. I mean, I simulated single FPGA working as two chips, and connected them so that they could transfer traffic to the other side. I also connected their logical ports to an "Arbiter" which will forward the traffic to the physical output Ethernet ports on "First in First out" basis. As i simulate all this on single FPGA, so I have logic to implement the Arbiter, which is the important stage of this design. And in simulation all is going fine.Below is the simulated experiment. I want to do it in real ASIC and FPGA now.

I just want to know that is it possible in real ASIC and FPGA to connect them both to the same physical output ports? If yes, then where can we implement the output queue which will buffer the packets coming from both ASIC and FPGA (after processing) and release in FIFO order towards output eth ports. Because here we do not have the "Arbiter" to forward the traffic coming from both the switching chips on some basis e.g. FIFO.

Two ways I thought about is, 1) Port Buffered Memory and 2) Shared Memory (SRAM, DRAM) could be the solution. Or any other better idea you can give. Thanks

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closed as unclear what you're asking by pjc50, Finbarr, Michel Keijzers, Voltage Spike, RoyC Apr 6 '18 at 20:59

Please clarify your specific problem or add additional details to highlight exactly what you need. As it's currently written, it’s hard to tell exactly what you're asking. See the How to Ask page for help clarifying this question. If this question can be reworded to fit the rules in the help center, please edit the question.

  • \$\begingroup\$ The question as it stands now is pretty messy. I understand the following: You have 2 blocks in your hardware which work side by side but have an identical output interface to the real world. In simulation you route the two outputs through an arbiter which does the eventual communication to the outputs over ethernet. This works in simulation but now you want to go to an actual implementation but cut out the arbiter? The only way I see the ASIC come into play is as the implementation of one of the two blocks, I guess? \$\endgroup\$ – DonFusili Apr 6 '18 at 10:26
  • \$\begingroup\$ Yeah, you got the scenario right sir. Actually the traffic will come from both the ASIC and FPGA. So where can i implement a queue, which will buffer the packets going to physical eth ports and leave in FIFO. Otherwise wouldn't they collide at the output port? \$\endgroup\$ – Khattak Apr 6 '18 at 11:16
  • \$\begingroup\$ In the simulator you need an arbiter, why do you think you wouldn't need one in real life? \$\endgroup\$ – immibis Apr 7 '18 at 6:56
  • \$\begingroup\$ @immibis , yes i would need, but for Arbiter means i would need a memory, where i could buffer the packets to release in FIFO, so where could i implement that memory, Port buffer or Shared buffer, as i mentioned above? \$\endgroup\$ – Khattak Apr 8 '18 at 7:47
  • \$\begingroup\$ why closed? i think it is pretty well explained, but the folks are unable to understand the scenario right. they need piece of cake in their mouth. \$\endgroup\$ – Khattak Apr 12 '18 at 6:41
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There are ways to do this, but you'd quickly end up fiddling with tristate buffers and the like. Just putting the wires together will create multiple drivers on lines and blow up pins in no time.

A nicer solution would be to route the ASIC output through the FPGA and implement both the block that you would have in the FPGA and the arbiter there. Then the FPGA has the only output towards the Ethernet. Assuming your arbiter is already synthesizable, this is a small change in code. This probably requires some redesign of the rest of your project, though, so consider other solutions.

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  • \$\begingroup\$ Note: this answer assumes your arbiter used for simulation is already written in an HDL. \$\endgroup\$ – DonFusili Apr 6 '18 at 11:29

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