I am doing simulation of my research design on single FPGA, in which I simulated two switching chips ASIC and an FPGA. I mean, I simulated single FPGA working as two chips, and connected them so that they could transfer traffic to the other side. I also connected their logical ports to an "Arbiter" which will forward the traffic to the physical output Ethernet ports on "First in First out" basis. As i simulate all this on single FPGA, so I have logic to implement the Arbiter, which is the important stage of this design. And in simulation all is going fine.Below is the simulated experiment. I want to do it in real ASIC and FPGA now.
I just want to know that is it possible in real ASIC and FPGA to connect them both to the same physical output ports? If yes, then where can we implement the output queue which will buffer the packets coming from both ASIC and FPGA (after processing) and release in FIFO order towards output eth ports. Because here we do not have the "Arbiter" to forward the traffic coming from both the switching chips on some basis e.g. FIFO.
Two ways I thought about is, 1) Port Buffered Memory and 2) Shared Memory (SRAM, DRAM) could be the solution. Or any other better idea you can give. Thanks