# Maximum frequency for a FPGA-based square wave signal

I have an understanding problem what is the maximum possible frequency for a square wave signal that can be generated.

I am currently experimenting with a FPGA board (Red Pitaya), which has a 125Mhz Xilinx Zynq FPGA. When I am connecting the clock signal via a Binary Counter and Slice (Xilinx IPs) for the bit #0 and to an output pin, I measure about the half frequency (62,5Mhz).

Here is the Xilinx Vivado block diagram
(32bit Binary Counter in UP-mode, 1bit Slice Din From + Din Down To are both 0):

I would have expected that I will see exactly the clock frequency on the output port.

Can someone please explain me why the frequency got halved and what is the maximum square wave frequency that can be created by a FPGA?

• What function generator? Commented Apr 6, 2018 at 10:23
• Just the clock signal (square wave with 50% duty cycle) Commented Apr 6, 2018 at 10:24
• What function generator (are you using)? Commented Apr 6, 2018 at 10:37
• Then your question is confusing because folk will take "function generator" as a bought item of equipment. Please change your question to be specific. Commented Apr 6, 2018 at 10:42
• Could you share any relevant code? Commented Apr 6, 2018 at 10:56

You can't generate a frequency higher than the internal clock. If you have access to a Phase Locked Loop or PLL, you might be able to.

Usually the external clock gets fed into an PLL and the internal clock is generated from that.

If your internal clock is 125Mhz and your using a regular counter (counting on only the rising edge), the fastest counting you will see will be at half of 125Mhz or 62.5Mhz.

Counters can be built that work on the rising and falling edge to give you counting at 125Mhz

• To expand on this, Xilinx recommends using the ODDR primitive to forward clocks. It gives better results than mucking with posedge and negedge statements. Commented Apr 6, 2018 at 16:34

If you don't feed the clock out with a DDR flip flop, then the max frequency you would expect to see is $f_{clk}/2$. The reason for this is that the output can only change once for every complete clock cycle (one rising edge and one falling edge). Additionally, this is what you would expect to see from a free-running binary counter...bit 0 (the LSB) will oscillate at $f_{clk}/2$, the bit 1 at $f_{clk}/4$, etc. If you want a higher frequency output, then you need to do two things: use a faster clock, and use DDR output registers. I have successfully driven outputs at 250 MHz and 500 MHz using DDR output registers.

All Xininx FPGAs (from series 3,4,5,6,7 etc.) offer extensive digital clock management (DCM) blocks that obviously include PLLs/DPLLs. In recent offerings these blocks are called MMCM - Mixed-Mode Clock Manager. There are several blocks in each FPGA, allowing many clock domains in a design. The Zynq/Artix FPGAs/SoC can have internal clocks running up to 800 MHz internally, down to 5 MHz, all easily derived from nearly any external clock.

The output capability depends on the selection of output buffer type, depending on buffer type and mode/strength selection. I believe 200-300-400 MHz of square wave is easily achievable, at least they can do it for DDR interfaces.