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Let's say I want to create this active low decoder:

+-----------------------------+
| E1 | E2 | a | b | 1 | 2 | 3 |
+-----------------------------+
|  x |  0 | x | x | 1 | 1 | 1 |
|  0 |  x | x | x | 1 | 1 | 1 |
|  1 |  1 | 0 | 0 | 1 | 1 | 1 |
|  1 |  1 | 0 | 1 | 0 | 1 | 1 |
|  1 |  1 | 1 | 0 | 1 | 0 | 1 |
|  1 |  1 | 1 | 1 | 1 | 1 | 0 |
+-----------------------------+

However I only have one-, two-, and three- input NAND gates. Would the circuit in the attached image be the minimum amount of components I can use?

The equations I used to create the circuit are:

\$1 = \overline{\overline{E_1a}\cdot\overline{E_2\overline{b}}}\$

\$2 = \overline{E_1\overline{a}}\cdot\overline{E_2\overline{b}}\$

\$3 = \overline{\overline{E_1\overline{a}}\cdot\overline{E_2\overline{b}}}\$

Here is the circuit that I got, is there a way to simplify it further? Here is the circuit that I got, is there a way to simplify it further?

Thank you so much!

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  • 3
    \$\begingroup\$ !!! KARNAUGH MAPS !!! is literally the answer to every question that has to do with digital logic circuit reduction... 100% of the time, K-Maps will help you :) Good luck! \$\endgroup\$ – KingDuken Apr 7 '18 at 2:52
  • \$\begingroup\$ @KingDuken But how do you use K-Maps while trying to preserve specific inputs (E1, E2, a, b)? \$\endgroup\$ – Switching Systems Apr 7 '18 at 4:41
  • \$\begingroup\$ You have drawn the Truth Table. From there, you can start drawing your K-Map. The inputs are quite literally what you place on your K-Map, that's how it's performed. \$\endgroup\$ – KingDuken Apr 7 '18 at 16:07
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I think the set of equations you have used are not correct. As per my understanding output must be "111b" if any of the inputs "E1" or "E2" is "0". The set of equations you have derived

"1" = ((E1a)'·(E2b')')'

"2" = ((E1a')'·(E2b)')'

"3" = ((E1a')'·(E2b')')'

returns "000b" for inputs with "E1 + E2 = 0" i.e. both of them are "0". Correct equations would be

Correct equations

and the corresponding circuit is Decoder Circuit This may not be the most optimized circuit but this is the minimum sized (area of all gates is 16 times area of the minimum sized inverter) circuit I came up with.

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  • \$\begingroup\$ This is good stuff, but the OP is obligated to use NAND gates as inverters. Yea, a one input NAND gate... \$\endgroup\$ – Sparky256 Apr 7 '18 at 6:20
  • \$\begingroup\$ Since almost all modern digital logic is implemented in CMOS technology I prefer to use the term/symbol "Inverter" instead of "One-input NAND gate". \$\endgroup\$ – Yogesh Apr 7 '18 at 6:30
  • \$\begingroup\$ It was the OP's instructor who came up with irrational parts to 'build' with. Such is life... \$\endgroup\$ – Sparky256 Apr 7 '18 at 6:32
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Since E1 and E2 are mutual enables you can delete E2 by connecting it to E1. Other than that you did a good job with what you had.

Of course any 74138/74HC138/74AC138 decoder will give you 8 states in a 14 pin DIP or SOIC. You should study that IC. It is very close to what you have, just more of it.

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  • \$\begingroup\$ If E2 is a requirement of the build (can't remove it) then this would be the best design possible preserving E1, E2, a, and b as inputs right? \$\endgroup\$ – Switching Systems Apr 7 '18 at 4:42
  • \$\begingroup\$ That would be correct if you are obligated to build with what you have. A one input NAND gate does not exist in the real world. IRL a inverter would be used along with 3 or 4 input NAND gates, as show in the answer below. The instructor gave you an irrational construction layout on purpose. \$\endgroup\$ – Sparky256 Apr 7 '18 at 6:24
  • \$\begingroup\$ The instructor wanted to see if you could work out the logic table and connections. Whether the parts actually exist to buy did not matter. \$\endgroup\$ – Sparky256 Apr 7 '18 at 6:30

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