# Ideal integrator op-amp DC offset at output?

i have a question with this ideal op-amp integrator circuit

where R=1k and C=1uF. Then i put a 50mV 100Hz square wave at the input and get the following response, which is what i expected and calculated beforehand.

(I'm aware that this is not a real practical integrator and this question has been taken account before making this post.)

The thing is, that you can see some sort of "DC offset" which I'm being questioned on why is it there. My explanation would be that when i have an input pulse, the op amp would have to drain (or supply) current through the capacitor and resistor in order to achieve the voltage across the resistor and sustain the virtual ground. This current is constant, hence charge in the capacitor grows linearly and so does voltage. Assuming the capacitor is initially discharged, the first pulse charges it to a value A and the contrary pulse discharges it to zero. A and then zero, A and then zero and so on in a triangular symmetrical way, so the average voltage is A/2. Of course the output voltage is the capacitor voltage because of the virtual ground.

At every cycle the voltage starts/ends at zero since the integral of every whole cycle of this signal is zero, that makes sense too.

I don't know why this "DC offset" wouldn't be there as it makes sense, but still my answer is not taken as valid. Is there some transient response I'm not seeing? Would the signal start at t=-infinity change anything?

The initial condition at the start of the simulation is computed by the simulator by inserting conductances (with value gmin) to ground. It is thanks to this it "knows" that the output of the amplifier will start at 0 Volt at t=0.

To change the initial condition you can either insert a load resistor to the desired voltage, or you can (in most simulators) override the initial condition with an .IC statement.

If you are happy with 0 Volts as the initial condition and the average (DC) value, then you need to change the phase of the square wave so the first edge comes after 1/4 of the period.

The 1st half of square wave is +ve so 1st ramp is negative.

But after 1 alternating square wave cycle, the Integrator output returns to 0.

So the result depends on the starting phase of input.

If the start was midpoint of high level then it would ramp negative then positive to 0 in 1/2 cycle and continue +ve then -ve back to zero after 1 cycle. This phase shift represents 0 DC offset because integrators also lag 90 deg.

-_-

Well, the answer was parasitic shunt resistance. That shouldn't allow the capacitor to have a steady average value since it would eventually fade away as an RC response.

I thought it was an ideal circuit too, but apparently it wasn't.