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I design 4 layer PCB (Top - Signal layer , Layer2 all voltage (2V8, 1V1...), Layer3 GND, Bottom - Signal Layer) I'm considering what should i do with free space on Top and Bottom. I always filled them with GND (It can remove crosstalk) but recently I heard that i should use gnd planes only in those places where i need to provide return path. So if i have gnd plane on layer 3 which covers whole circuit area there i should fill free spaces on top and bottom via gnd plane? I also know that the manufacturers recommended to ensure provide an equal field of copper on every layer to prevent from bending during soldering. What do you think?

My pcb: enter image description here enter image description here

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  • \$\begingroup\$ As can you see on the pictures I add some gnd and other signal planes to ensure equal field of copper (On Top layer) \$\endgroup\$ – M.Kruk Apr 8 '18 at 18:25
  • \$\begingroup\$ Are you worried about high frequency coupling from traces to adjacent ground pours? Pouring ground everywhere is an issue if the poured areas are insufficiently connected to internal GND planes (e.g. long stubs that can radiate), or allow very high frequency signals couple where they should not. \$\endgroup\$ – Zekhariah Apr 8 '18 at 19:18
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I try to keep it short:

First of all, for a 4 layer PCB, try to put the middle GND plane near to the plane carrying most sensitive or "fast" components in order to shorten the critical vias from the components to this middle plane.

Whether or not you want to fill TOP/BOTTOM free space with GND depends on how segmented this GND fills will be and how good you can stitch them to the middle (solid) GND plain. If you fill these free spaces, then also try to provide a lot of stitching vias, especially on the edges of the board (building a "cage"). Because if you have a big TOP/BOTTOM filling with only one stitching via to the middle (solid) plane, this acts like a "patch" type of antenna.

For a 4 layer PCB in general, I would not recommend TOP/BOTTOM fills.

Keep in mind this general rule: You must provide the lowest possible resistance path for current to flow from each IC's VCC to GND pin.

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