Why do we have four instructions in IT block for Cortex M4 processor? Is it related to the fact that we have three pipelines for ARM assembly instructions?


Quoting from ARM's information center about the Cortex M4:

IT{x{y{z}}} cond where:

x Specifies the condition switch for the second instruction in the IT block.

y Specifies the condition switch for the third instruction in the IT block.

z Specifies the condition switch for the fourth instruction in the IT block.

cond Specifies the condition for the first instruction in the IT block.

The condition switch for the second, third and fourth instruction in the IT block can be either:

T Then. Applies the condition cond to the instruction.

E Else. Applies the inverse condition of cond to the instruction.

The IT instruction makes up to four following instructions conditional. The conditions can be all the same, or some of them can be the logical inverse of the others. The conditional instructions following the IT instruction form the IT block.

The instructions in the IT block, including any branches, must specify the condition in the {cond} part of their syntax.

Read more here... This is where I got the information from.


Usually there are at least two shorthand IT (If-Then) instructions, to be able to efficiently execute these C constructs:

If with no else-branch (IT: If-Then): if (X) { /* do something */ }

If with an else-branch (ITTE: If-This-Then-Else): if (X) { /* do something */ } else { /* do something else */ } C

Not sure about the other ones.


It's based on the pipeline length and the number of bits that were available in the opcode.

Branching causes a bit of a hiccup in the pipeline, so it is more efficient to skip some instructions by making them conditional. However, all of these instructions still need to be fetched and partially decoded, so if the conditional block is longer than a few instructions (depending on the exact version of the ARM architecture), a branch is still more efficient.

Typical ARM code often has constructs like

   CMP …
   ADDLT …
   LDRLT …
   LDRGE …

which is both shorter and faster than the branched variant

   CMP …
   BGE 1f
   ADD …
   LDR …
   B 2f
   LDR …

However, for five or more instructions, the branch is cheaper and the space saving gives you diminishing returns.

Thumb moves the condition field into a separate instruction, but the economics of when it is cheaper to skip or branch remain roughly the same. Using more opcode bits to allow skipping more instructions only gives minimal space savings, while fewer conditional instructions would force the compiler to generate a branch in Thumb code where it would have used conditionals in 32 bit ARM code.


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