simulate this circuit – Schematic created using CircuitLab

For all intents and purposes lets assume this basic power stage of a synchronous buck design above. Let's also assume a steady state operating condition.

When in steady state, it can be shown that a portion of the inductor current in this particular circuit is negative. My question is - given this "light load" condition, and given an gate drive IC that does not account for any sort of pulse skipping, diode emulation etc, how can a constant current of ~33mA be delivered when the SW2 is "closed" and SW1 "open"?

My initial thoughts are that C1 is supplying the energy necessary to keep the load ~33mA. Given that


We can estimate the amount of total charge the capacitor has stored. But how long can that capacitor supply energy to the load "R1" before the switching cycle must restart? Isn't charge flowing from C1 to GND through SW2 as well?

I'm aware that there is ripple associated with these values - however in an attempt to simplify the matter i have left them out. I am just trying to better understand the load current given "light load" conditions above. Thanks for the help.

  • \$\begingroup\$ I've seen the discontinuous-mode used, where both switches are opened. Enormous ringing results at the switch node. \$\endgroup\$ Apr 10, 2018 at 3:36
  • \$\begingroup\$ I don't understand why you think there is any problem. In the steady state, Vout = Vin * duty cycle. Period. It doesn't even matter if Iout is positive or negative. Maybe you should simulate this and look at the various currents and voltages and try different values of inductor and capacitor. As the inductor gets bigger, the ripple current gets less, and once the ripple is less than the average current, the current in the inductor will never reverse. \$\endgroup\$
    – mkeith
    Apr 10, 2018 at 3:46
  • \$\begingroup\$ If you simulate it, just use a pulse generator instead of the 12V supply, and set up the duty cycle of the pulse to be 3.3/12. Run the simulation long enough for steady state to occur. Adding small series resistance to the inductor and capacitor will help keep the ringing down to manageable levels. \$\endgroup\$
    – mkeith
    Apr 10, 2018 at 3:48
  • \$\begingroup\$ @mkeith You're missing the point. At light load you will enter DCM eventually and Vout is not longer Vin*duty cycle. \$\endgroup\$
    – winny
    Apr 10, 2018 at 10:21
  • \$\begingroup\$ @winny, in a synchronous, fixed frequency buck with constant current load, Vout = D * Vin. Even if the load current is zero. I don't believe I am wrong about that. \$\endgroup\$
    – mkeith
    Apr 10, 2018 at 15:29

3 Answers 3


You should read some app notes on buck regulators.

The starting point for a buck regulator is often the inductor. A key equation for steady state of a synchronous buck is that Vout = D * Vin, where D is the duty cycle (percent high time of the switching node).

Duty cycle / switching frequency gives you the duration of the high pulse. Let's call this high time Thi.

The ripple current in the inductor is determined using V = L*(di/dt).

V is the voltage across the inductor when switch node is high (Vin-Vout). L is inductor value. dt is Thi. And di is the ripple current we are solving for.

di = (Vin-Vout) * Thi / L

If the ripple is less than twice the load current, the inductor current will never reverse. In your case, if the ripple current is less than 66mA, the inductor current will never reverse. If the ripple current is more than 66mA, then it will eventually reverse. But in a syncrhonous buck regulator, reversing current will not necessarily cause any problem (depending on the regulation scheme used). You could say that this is not going to be an efficient mode of operation, and that is for sure true. So typical regulators will do something when this happens to try to gain some efficiency.

One thing I would like to point out is that a synchronous buck, depending on the control algorithm, is potentially stable and able to maintain output voltage regulation even when the load current is negative (flowing from load into buck, instead of into load). And in this condition, the steady-state duty cycle equation is exactly the same. Vout = D * Vin.

In this case, the average inductor current will be in the reverse direction. Obviously, if current is flowing INTO Vin, it is essential that Vin be able to accommodate that current or else the voltage will start to rise.

The other point worth noting is that when the load is constant, the output voltage of a buck will always converge on Vin * D, even if there is no output voltage feedback. If you change the load current, there may be a very undesirable response (ringing and overshoot or undershoot) but it will eventually converge on Vin * D.

The output capacitor does need to be big enough to reduce output ripple voltage to a reasonable level. Otherwise none of the above analysis will necessarily apply. I am not going to go through that, though.


The two switches (and their respective duty cycle) generate a square wave whose average value is that which is required at the output. If you want 3.3 volts at the ouput then, to make a square wave with an average value of 3.3 volts given that the input DC voltage is 12 volts, you need a duty cycle that is 0.275 then

\$\dfrac{3.3}{12} = 0.275 = D\$.

The L & C form a low pass filter and converts the rectangular wave (average value of 3.3 volts) into a steady 3.3 volts (with a small amount of ripple).

enter image description here

How synchronous buck converters continue to operate in light load conditions

A synchronous buck converter like this will produce the correct voltage irrespective of load current and, even if the load current is quite high, providing the MOSFETs used for the switching are low on-resistance, Vout will remain largely unchanged.


More and more PWM control IC's implement a 'pulse-stealing' technique by which they begin to cut off pulses to the MOSFET's on a scale based on how light the load is.

In other words it will cut off as many pulses (not consecutively) as needed to keep the output voltage stable.

This has one bad side effect, and that's if the bypass capacitors are not large enough to fill in the gaps between pulses then the output starts to pulse itself, in the form of a ripple.

However, assuming bypass capacitor is large enough then these are ideal solutions for micro-power devices that may need only uA to idle or sleep, then many mA when they wake up.

This IC does pulse stealing as required.

enter image description here

This link offers some details on pulse stealing.


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