I'm doing some theoretical design for a simple dsPIC-based ADC circuit. Both the device specsheet DS70000657H-page 30 and application note Analog and Interface Guide say that:

  • AVdd and Vdd can be connected via a choke
  • AVss and Vss must be connected directly, but you can have two planes that are spatially and electrically separated in the vicinity of their circuit sections, with separate return traces that are connected at the voltage source

Of particular interest:

DS70000657H-page 30 figure 2-1

My ADC conversion rate is very low (on the order of 5 Hz). If I use that frequency, the required values for L and C are very high. To allow reasonably inexpensive parts, using an aluminium 100uF capacitor for AVdd and a 33uH choke, I would have to sample at ~2.8 kHz, which is too fast.

My questions are:

  • Is the ADC conversion rate referenced in the specsheet an exact rate, or a maximum rate below which sampling is safe?
  • If the physical sampling rate is non-negotiable, could I use it but then run an internal DSP, such as moving average filter?
  • \$\begingroup\$ Given your sample rate is so low, I would size the inductor for blocking any high-f noise from other circuits in your system not for the sample rate itself. \$\endgroup\$ – Tom Carpenter Apr 10 '18 at 16:31
  • \$\begingroup\$ Or simply use something like a feed-through capacitor instead. \$\endgroup\$ – Tom Carpenter Apr 10 '18 at 16:32
  • \$\begingroup\$ And I would also ignore the suggestion to split the planes (some good reading). \$\endgroup\$ – Tom Carpenter Apr 10 '18 at 16:33

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