Here is a simple circuit that I simulated with LTSpice using UniversalOpamp2 component. C1 was initially added to remove DC voltage on inverting input. Sinus has a 0 offset, so C1 seems unneeded, but I kept it because I observed unexpected simulation results.
In this inverting configuration with a 1 gain, I expected an output of 5V - sine input. In simulation I get 2.5V - sine input, C1 capacitor removes 2.5V from dc offset on output. Why?
EDIT : From calculations, I we get this formula for :
Vout = 2.5*(1+R2/(R1 + 1/jC1w)) - Vin*R2/(R1 + 1/jC1w)
Said in others terms, offset and Vin have same gain
G = R2/(R1 + 1/jC1w), only sign changes.
But offset on positive input, as a DC component has only a 1 gain as R2/(R1 + 1/jC1w) is 0 for a DC signal.
At 1kHz, Gain for sine should be
100k/sqrt(100k^2 + 1/(2*pifC1)^2) = 0.78.
That corresponds to our max voltage of 3.3V ~ 2.5+1*0.8
So to sum up... do not forget reactance when calculating opamp gain!