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For something so common, I can't seem to find anything online on what a microcontroller pin "looks like" (besides a high-level voltage source when output, open-circuit when input). So I decided to just do it myself - let me know what you think. Obviousy specs as per transistor characterstics, pull-up value, etc. aren't important for this.

enter image description here

Functionality:

  1. State (Input or Output):

    • When 0V, input (just like code), Q1 is off and output voltage is disconnected
    • When 3.3V, output (just like code), Q1 is on and output voltage is connected to the pin

  2. Output:

    • When 0V, low, outputs 0 volts (duh)
    • When 3.3V, high, outputs 3.3 volts (duh)
    • Only makes it to the pin if state is high

  3. Input:

    • High-Input impedance straight into gate
    • If 0V, Q4 is off and so "input" port will read 0V or low
    • If 3.3V, Q4 is on and so "input" port will read 3.3V or high

  4. Pull-Up / Pull-Down

    • If they are 3.3V, connects the pin to a pull-up or pull-down resistor.
    • If they are 0V, FET is off and so the resistor is floating there not affecting the circuit

Thoughts? In terms of anything maybe missing / unnecessary. The state and pull-up N-Fets probably aren't necessary - they are just there to make the logic not inverted and the system easier to understand.

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  • \$\begingroup\$ Pretty much, yes. \$\endgroup\$
    – user253751
    Apr 11, 2018 at 5:20
  • \$\begingroup\$ Slightly more accurate if you use a 4-terminal symbol for Q1 and tie the back gate to vdd instead of to the source. \$\endgroup\$
    – The Photon
    Apr 11, 2018 at 5:40
  • \$\begingroup\$ this other EE.SE thread has some relevant info. \$\endgroup\$
    – Lorenzo Donati support Ukraine
    Apr 11, 2018 at 6:00
  • \$\begingroup\$ Add some ESD clamp diodes? And you might want to model some series L and shunt C at the pin if you are concerned about SI issues. \$\endgroup\$
    – Dan Mills
    Apr 11, 2018 at 10:04
  • \$\begingroup\$ Add in 1 or 2 nanoHenry, for onchip and bondwire and leadframe and PCB traces, at a minimum. And 5pF to 10pF to each of GND and VDD. Note this is a resonant circuit, with unknown dampening. Ringing will happen. What will you do? Your data-eyes will be degraded. \$\endgroup\$
    – analogsystemsrf
    Apr 12, 2018 at 4:46

1 Answer 1

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The logical diagram will very depending on the MCU you consider.

The ATMega328 datasheet shows a logical diagram of a GPIO pin in section 18.2 you might use as a general introduction.

enter image description here

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  • \$\begingroup\$ Yeah I figured that - for example, AVR's don't usually have pull-downs but ARM chips do (hence one lacking on the diagram you have. I wasn't talking about a logical diagram - I meant still at a "somewhat" high-level, how it behaves functionality wise with transistors (output high vs output low vs input vs pull-ups). That is, not worrying about timing / clock / wake-ups / ADC / etc. \$\endgroup\$
    – DSWG
    Apr 11, 2018 at 5:03

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