This is a capacitive moisture sensor circuit. C1 is the equivalent capacitor it tries to measure. Input v1 with 54.7% duty cycle is a square wave generated by a 555 timer. Output is v3 (point 3 in the graph to GND).

enter image description here

I tried to represent the square wave as Fourier series and use impedance model to find the steady state output. However, it seems that the diode is the key here but I don't know how to get the impedance of that diode.

Ultimately I'm trying to understand how to analyze this circuit and get the relationship between C1 and V3. I'm guessing there is an entirely different way other than the impedance model?

Thanks for any help!

  • \$\begingroup\$ Use a simulator is my advice. \$\endgroup\$
    – Andy aka
    Commented Apr 12, 2018 at 8:27
  • \$\begingroup\$ @Andyaka, in fact the graph is from multisim. I got the result, v3 surly is changing with change in C1. But I want to get the mathematical representation of the relationship or at least understand why the circuit is designed that way. Thanks anyway: ) \$\endgroup\$
    – gordon
    Commented Apr 12, 2018 at 8:44

1 Answer 1


Here is my attempt to analyze this, but I'm not doing a very theoretical solution:

I've redrawn the circuit, and that made the structure and working principle for me much clearer:


simulate this circuit – Schematic created using CircuitLab

So I can split that circuit basically in two parts:

  1. a low pass filter formed by R1 and C1
  2. a peak detector circuit formed by D1 C2 and R2

The low pass filter has a time constant of \$\tau = R_1 \times C_1\$. As C1 and R1 are not overly large, you won't get enough filtering of the input square wave to get a nice and clean DC voltage out of it. Tau is in the order of 1 µs, so it's close to the input frequency and not much higher. This results in a output with high voltage ripple.

That is where the second circuit comes to play. It is a peak detector circuit, so it will keep the maximum voltage of the ripple minus the diode voltage drop.

Note that the size of C2 is probably chosen in a way to allow an ADC to get a sample out of it, from a theoretical standpoint it could be much smaller, but the electronics behind might draw some current from it and you don't want the voltage to drop too far.

So what is the relation of the input capacitance and the voltage of the peak detector?

Let's do a little thought experiment and consider two extreme cases:

  1. C1 is 0 pF

The output of the low pass filter will obviously be just the input voltage, as the low pass filter is effectively just the resistor. So the output at node 3 will be the square wave peak voltage minus the diode voltage (around 2.4 V).

  1. C1 is very very large

Now the low pass filter has a very large time constant. In the long run it will settle at the average voltage of the input signal. Around 1.64 V in this example (54,7% of 3V). And the output will be this minus the diode drop, so around 0.9 V to 1 V (depends strongly on the diode).

So what have we learned by this?

The output voltage is inversely proportional to the capacitance of C1, the smaller C1 the higher the output voltage.

To get the exact relationship you have to calculate the maximum voltage of the low pass filter ripple voltage in dependence of the capacity of C1. I guess there is a formula out there, but I don't have it right now and not the time to spend further research into this currently.

I still think this might help you on your way to the answer.

  • \$\begingroup\$ It conforms with the simulation result. I'll try to get a numerical relationship. Thanks very much! There is one more question that still troubles me though. comparing to other method of measuring the capacitance of c1, what is the advantage of this method? \$\endgroup\$
    – gordon
    Commented Apr 12, 2018 at 10:06

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