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Now, I've been learning Verilog but I got stuck with some easy problems.
always@(posedge clock)
if(reset == 1’b1) leds_r <=0;
else leds_r <= leds_r + 1;
I can understand if(reset==1'b1)leds_r<=0;
but the matter is else leds_r <= leds_r+1; what is that means?
I activated that with only always@(posedge clock) leds_r <=leds_r+1; code
using Spartan-3A/AN Starter Kit Board then, after I pushed reset button, all the leds were cleared.
It is essentially the meaning behind Register Transfer Level(RTL) abstraction coding. You are describing the transfer of data to registers at each clock cycle. The English translation of the code would be:
At the rising clock edge, if
resetis true the registerleds_rgets the value0, otherwise, the registerleds_rgets the current value of the expressionleds_r + 1
leds_rchanges from whatever value it had to one more than that. It's the usual way to express a counter in Verilog. \$\endgroup\$<=means non-blocking assignment. I.e. it is basically saying incrementleds_rby 1. \$\endgroup\$