Now, I've been learning Verilog but I got stuck with some easy problems.
always@(posedge clock) if(reset == 1’b1) leds_r <=0; else leds_r <= leds_r + 1;
I can understand
but the matter is
else leds_r <= leds_r+1; what is that means?
I activated that with only
always@(posedge clock) leds_r <=leds_r+1; code
using Spartan-3A/AN Starter Kit Board then, after I pushed reset button, all the leds were cleared.