# verilog register with clock

Now, I've been learning Verilog but I got stuck with some easy problems.

always@(posedge clock)
if(reset == 1’b1) leds_r <=0;
else leds_r <= leds_r + 1;


I can understand if(reset==1'b1)leds_r<=0; but the matter is else leds_r <= leds_r+1; what is that means?

I activated that with only always@(posedge clock) leds_r <=leds_r+1; code using Spartan-3A/AN Starter Kit Board then, after I pushed reset button, all the leds were cleared.

• 'else' is a computer programming word for 'otherwise'. Apr 12, 2018 at 17:21
• I mean, I can't understand leds_r <=leds_r+1; I'm sorry I forgot adding passage reg [27:0] leds_r; Apr 12, 2018 at 17:29
• It means the register leds_r changes from whatever value it had to one more than that. It's the usual way to express a counter in Verilog. Apr 12, 2018 at 17:30
• <= means non-blocking assignment. I.e. it is basically saying increment leds_r by 1. Apr 12, 2018 at 18:37

It is essentially the meaning behind Register Transfer Level(RTL) abstraction coding. You are describing the transfer of data to registers at each clock cycle. The English translation of the code would be:

At the rising clock edge, if reset is true the register leds_r gets the value 0, otherwise, the register leds_r gets the current value of the expression leds_r + 1